On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.

Networks on chips: a new SoC paradigm

저작근 근전도에 관한 정상교합자와 ii급 부정교합자의 비교 연구

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 /spl mu/m technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%).

Razor: a low-power pipeline based on circuit-level timing speculation

Low-power and high-throughput Viterbi decoder (VD) for tail-biting convolutional codes is presented in this paper. First, a low complexity radix-4 VD with enhanced decoding features such as end-state forcing and best-state trace back is presented. Second, simple predecoding is proposed to decrease the runtime of VD, resulting in significant power saving. The design is implemented in 0:9V TI 45-nm CMOS process at 100MHz for Long Term Evolution (LTE) [1] as application. More than 90% power saving is achieved with predecoding at a throughput of 120 Mbps and 0:2 dB SNR loss for 10−5 frame error rate.

/pdf/low-power-pre-decoding-based-viterbi-decoder-for-tail-biting-5dbt6w5a3b.pdf

Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes

Presented in this paper are decorrelating transformations (referred to as DECOR transformations) to reduce the power dissipation in adaptive filters. The coefficients generated by the weight update block in an adaptive filter are passed through a decorrelating block such that fewer bits are required to represent the coefficients. Thus, the size of the arithmetic units in the filter (F-block) is reduced thereby reducing the power dissipation. The DECOR transform is well suited for narrow-band filters because there is significant correlation between adjacent coefficients. In addition, the effectiveness of DECOR transforms increases with increase in the order of the filter and decrease in coefficient precision. Simulation results indicate reduction in power dissipation in the F-block ranging from 12% to 38% for filter bandwidths ranging from 0.15 f/sub s/, to 0.025 f/sub s/, (where f/sub s/ is the sample rate).

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1998/islped98/pdffiles/t6_1.pdf

Decorrelating (DECOR) transformations for low-power adaptive filters

A new circuit technique, referred to as the twin-transistor technique, for increasing the noise immunity of dynamic logic circuits is presented. This technique makes dynamic logic gates more tolerant to noise appearing at the gate inputs. A multiply-accumulate circuit has been designed and fabricated using a 0.35 /spl mu/m process to verify this technique. Experimental results indicate that the twin-transistor technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4 X) with only a modest increase in power dissipation (15%) and no loss in throughput.

A noise-tolerant dynamic circuit design technique

Modern integrated circuits (ICs) are designed as massively parallel systems as a consequence of diminishing silicon feature sizes. This has adversely impacted reliability because of increased errors due to process and environmental variations, and particle hits. Viewing hardware errors as analogous to measurement or system noise allows us to borrow results from estimation theory and extend Moore's law. The estimation-theoretic framework provides a design optimization formalization that enables power/reliability trade-off in broad classes of applications. Two applications described here show that specific instantiations of the framework yield significant power savings and system reliability.

Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption

A system includes a circuit having a plurality of electronic function blocks interconnected in series, a power source unit coupled to the circuit, for supplying power to the plurality of electronic function blocks, and a control unit coupled to each of the plurality of the electronic function blocks and to the power source unit. The control unit is configured to monitor activity levels of each of the electronic function blocks, and adjusts the activity level of each of the plurality of electronic function blocks. The control unit determines a voltage level suitable for the corresponding adjusted activity level, and adjusts the power supplied to each of the plurality of electronic function blocks in order to achieve the corresponding determined voltage level at each of the plurality of electronic function blocks.

Naresh R. Shanbhag

Papers

Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes

Decorrelating (DECOR) transformations for low-power adaptive filters

A noise-tolerant dynamic circuit design technique

Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption

System and method for improving power conversion for advanced electronic circuits