On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.

Networks on chips: a new SoC paradigm

저작근 근전도에 관한 정상교합자와 ii급 부정교합자의 비교 연구

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 /spl mu/m technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%).

Razor: a low-power pipeline based on circuit-level timing speculation

A low-power technique for digital filtering referred to as adaptive error-cancellation (AEC) is presented in this paper. The AEC technique falls under the general class of algorithmic noise-tolerance (ANT) techniques proposed earlier for combating transient/soft errors. The proposed AEC technique exploits the correlation between the input and soft errors to estimate and cancel out the latter. In this paper, we apply AEC along with voltage overscaling (VOS), where the voltage is scaled beyond the minimum (referred to as V/sub dd-crit/) necessary for correct operation. We employ the AEC technique in the context of a frequency-division multiplexed (FDM) communication system and demonstrate that up to 71% energy reduction can be achieved over present-day voltage-scaled systems.

Low-power filtering via adaptive error-cancellation

Relaxed look-ahead is presented as an attractive technique for pipelining adaptive filters. Unlike conventional look-ahead, relaxed look-ahead does not attempt to maintain the input-output (I/O) mapping between the serial and pipelined architectures but preserves the adaptation characteristics, resulting in a small hardware overhead. Relaxed look-ahead is employed to develop fine-grained pipelined architectures for least-mean-square (LMS) adaptive filtering. The proposed architecture achieves the desired speed-up, with little or no degradation in the convergence behavior. Simulation results verifying the convergence analysis results for the pipelined LMS filter are presented. The filter is then employed to develop a high-speed adaptive differential pulse-code-modulation (ADPCM) codec. The new architecture has a negligible hardware overhead which is independent of the number of quantizer levels, the predictor order and the pipelining level. Additionally, the pipelined codec has a much lower output latency than the level of pipelining. Simulations with image data indicate that speed-ups of up to 43 can be achieved with less than 1-dB loss in SNR. >

Relaxed look-ahead pipelined LMS adaptive filters and their application to ADPCM coder

Presented is an energy-efficient motion estimation architecture using error-tolerance. The technique employs overscaling of the supply voltage (voltage overscaling (VOS)) to reduce power at the expense of timing errors, which are then corrected using algorithmic noise-tolerance (ANT) techniques. Referred to as input subsampled replica ANT (ISR-ANT), the proposed technique incorporates an input subsampled replica of the main sum of absolute difference (MSAD) block for obtaining the motion vectors in the presence of errors induced by VOS. Simulations show that the proposed technique can save up to 60% power over an optimal error-free present day system in a 130nm CMOS technology. Power savings increase to 79% in a 45nm predictive process technology.

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Energy-efficient motion estimation using error-tolerance

Preface. 1. Introduction. 2. A Pipelined Adaptive Lattice Filter Architecture. 3. Relaxed Look-Ahead Pipelined LMS Adaptive Filters and Quantizers. 4. A Pipelined Adaptive Differential Vector Quantizer Architecture and a Design Algorithm. 5. Fine-Grain Pipelined Adaptive DFE Architectures using Relaxed Look-Ahead. 6. Finite-Precision Analysis of the Pipelined ADPCM Coder. 7. VLSI Implementation of a 100 MHz Pipelined ADPCM CODEC Chip. 8. A Pipelined Kalman Filter Architecture. 9. Future Research Directions. 10. References. Index.

Pipelined Adaptive Digital Filters

This paper provides an overview of algorithmic noise-tolerance (ANT) for designing reliable and energy-efficient digital signal processing systems. Techniques such as prediction-based, error cancellation-based, and reduced precision redundancy based ANT are discussed. Average energy-savings range from 67% to 71% over conventional systems. Fluid IP core generators are proposed as a means of encapsulating the benefits of an ANT-based low-power design methodology. CAD issues resident in such a methodology are also discussed.

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Naresh R. Shanbhag

Papers

Low-power filtering via adaptive error-cancellation

Relaxed look-ahead pipelined LMS adaptive filters and their application to ADPCM coder

Energy-efficient motion estimation using error-tolerance

Pipelined Adaptive Digital Filters

Reliable and energy-efficient digital signal processing