On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.

Networks on chips: a new SoC paradigm

저작근 근전도에 관한 정상교합자와 ii급 부정교합자의 비교 연구

As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 /spl mu/m technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%).

Razor: a low-power pipeline based on circuit-level timing speculation

Jitter significantly limits the maximum achievable data rates (MADR) over high-speed source-synchronous I/O links. In this paper, we present a simple model that comprehends transmitter and receiver jitter in a source-synchronous I/O link. We show that the channel can have a significant impact on transmit jitter at high data rates, resulting in 1.1X-3.8X jitter amplification for typical cases. We quantify the performance degradation of transmit/receive equalization and multilevel modulation schemes, due to jitter in high-speed I/O links. We present two design techniques to mitigate the effect of jitter on performance-transmission of a slower source-synchronous clock, and jitter equalization. Both techniques can improve MADR by 13% when signaling over a 20" FR4 channel.

Modeling and mitigation of jitter in high-speed source-synchronous interchip communication systems

In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies. We develop a methodology to calculate the repeater size and separation that minimize the total power dissipation for joint repeater insertion and coding for a specific delay target. This methodology is employed to obtain power vs. delay trade-offs for 130-nm, 90-nm, 65-nm, and 45-nm technology nodes. Using ITRS technology scaling data, we show that proposed technique provides 54%, 67%, and 69% power savings over optimally repeater-inserted 10-mm 32-bit bus at 90-nm, 65-nm, and 45-nm technology nodes, respectively, while achieving the same delay.

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A low-power bus design using joint repeater insertion and coding

Achieving energy-efficiency in nanoscale CMOS process technologies is made challenging due to the presence of process, temperature and voltage variations. In this paper, we present soft N-modular redundancy (soft NMR) that consciously exploits statistics of errors due to these nanoscale artifacts in order to design robust and energy-efficient systems. In contrast to conventional NMR, soft NMR employs estimation and detection techniques in the voter. We compare NMR and soft NMR in the design of an energy-efficient and robust discrete cosine transform (DCT) image coder. Simulations in a commercial 45nm, 1.2V, CMOS process show that soft triple-MR (TMR) provides 10× improvement in robustness and 13% power savings over TMR at a peak signal-to-noise ratio (PSNR) of 20dB. In addition, soft dual-MR (DMR) provides 2× improvement in robustness and 35% power savings over TMR at a PSNR of 20dB.

Soft NMR: Exploiting statistics for energy-efficiency

A pipelined architecture for adaptive pulse code modulation (ADPCM) is presented. The architecture is developed by the application of a realized form of look-ahead. The hardware overhead is only the pipelining latches and is independent of the number of quantizer levels, the predictor order, and the pipelining level. The codec latency is smaller than the level of pipelining. Under the assumption of small quantization error, the convergence properties of the pipelined architecture are compared with those of the serial one. Speech and image coding examples are presented to support the conclusions reached. >

A high-speed architecture for ADPCM codec

This paper presents the first integrated circuit implementation of
a Hermitian decoder thereby proving its practical viability. Hermitian
codes provide much larger block lengths (n=4080) compared to that of the
popular Reed-Solomon (RS) codes (n=256) over the same field (GF(256)).
This translates to a coding gain of 0.6 dB for the same rate. However,
Hermitian codes were deemed to be too complex to implement until the
emergence of a recent algorithmic breakthrough which made the complexity
of Hermitian decoders comparable to that of RS codes. Based on Koetter's
decoding algorithm, the chip architecture consists of an array of
sixteen interdependent Berlekamp-Massey algorithm (BMA) blocks. Thus,
the same IC can be used for decoding RS codes as well. The decoder IC is
designed in a 3.3 V, 0.35 μm, four-metal CMOS process and can correct
up to t=60 errors per block of n=4080 words at a rate of 400 Mb/s. The
IC prototype consumes 3.0 W with a 50 MHz clock

Naresh R. Shanbhag

Papers

Modeling and mitigation of jitter in high-speed source-synchronous interchip communication systems

A low-power bus design using joint repeater insertion and coding

Soft NMR: Exploiting statistics for energy-efficiency

A high-speed architecture for ADPCM codec

Implementation of a Hermitian decoder IC in 0.35 /spl mu/m CMOS