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Narumasa Soejima
Researcher at Denso
Publications - 57
Citations - 1130
Narumasa Soejima is an academic researcher from Denso. The author has contributed to research in topics: Layer (electronics) & Trench. The author has an hindex of 15, co-authored 57 publications receiving 1056 citations. Previous affiliations of Narumasa Soejima include Toyota.
Papers
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Journal ArticleDOI
GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching
Masahito Kodama,Masahiro Sugimoto,Eiko Hayashi,Narumasa Soejima,Osamu Ishiguro,Masakazu Kanechika,Kenji Itoh,Hiroyuki Ueda,Tsutomu Uesugi,Tetsu Kachi +9 more
TL;DR: In this article, a novel method for fabricating trench structures on GaN was developed and a smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant.
Patent
Silicon carbide semiconductor device and method of manufacturing the same
Naohiro Suzuki,Hideo Matsuki,Masahiro Sugimoto,Hidefumi Takaya,Jun Morimoto,Tsuyoshi Ishikawa,Narumasa Soejima,Yukihiko Watanabe +7 more
TL;DR: In this paper, the authors propose a silicon carbide semiconductor device consisting of a substrate, a drift layer, a base region, source region, a trench, a gate insulating layer, gate electrode, a source electrode, drain electrode and a deep layer.
Journal ArticleDOI
A Vertical Insulated Gate AlGaN/GaN Heterojunction Field-Effect Transistor
Masakazu Kanechika,Masahiro Sugimoto,Narumasa Soejima,Hiroyuki Ueda,Osamu Ishiguro,Masahito Kodama,Eiko Hayashi,Kenji Itoh,Tsutomu Uesugi,Tetsu Kachi +9 more
TL;DR: In this article, a vertical insulated gate AlGaN/GaN heterojunction field effect transistor (HFET) was fabricated using a free-standing GaN substrate, which exhibited a specific on-resistance of as low as 2.6 mΩ·cm2 with a threshold voltage of -16 V.
Journal ArticleDOI
DLTS study of n-type GaN grown by MOCVD on GaN substrates
TL;DR: In this paper, two free-standing HVPE GaN substrates (A and B) were obtained from two different sources, obtained from different sources using DLTS for vertical Schottky diodes.
Patent
Iii-v hemt devices
Masahiro Sugimoto,Tetsu Kachi,Yoshitaka Nakano,Tsutomu Uesugi,Hiroyuki Ueda,Narumasa Soejima +5 more
TL;DR: In this paper, the authors proposed a III-V semiconductor device with a gate electrode formed at the top surface side of the AlGaN layer 34, which has a band gap of 1.5x1017cm-3.