Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the world's first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.

BSIM—SPICE Models Enable FinFET and UTB IC Designs

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

BSIM compact models have served industry for more than a decade starting with BSIM3 and later BSIM4 and BSIMSOI. Here we will briefly discuss the ongoing work on current and future device models in BSIM group. BSIM6 is the next generation bulk RF MOSFET Model which uses charge based core with physical models adapted from BSIM4. Model fulfills all symmetry tests and shows correct slopes for harmonics. The BSIM-CMG and BSIM-IMG are the surface potential based models for multi-gate MOSFETs. The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFET. The BSIM-IMG model has been developed to model independent double-gate MOSFET capturing threshold voltage variation with back gate bias. Models include all read device effects like SCE, DIBL, mobility degradation, poly depletion, QME etc.

BSIM — Industry standard compact MOSFET models

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters.

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description

A detailed presentation of the latest version of the Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of low-doped ultrathin body and buried oxide fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this part, a full analytical calculation of interface potentials, valid for all regimes of independent double-gate device operation, is detailed. This analytical computation, which is the heart of Leti-UTSOI2, provides explicit expressions for all quantities required to build dc and ac core models.

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part I: Interface Potentials Analytical Model

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

O. Rozeau

Papers

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control