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Design Of Analog Cmos Integrated Circuits

Physical limitations for CMOS technology have provided the way for manufacturing the quantum cellular automata technology-based hardware elements at Nano level. From the purpose of very high speed, area and low power consumption, this Nanotechnology has been taken into consideration. Improving their structures will lead promoting the system performance completely, because the Full adders are assumed as major and primary component of computational processors. In current study, the new layout of all single bit full adders in the quantum cellular automata's technology is introduced. In comparison with existing schemes, the suggested circuit has fewer cells and smaller area.

A new quantum-dot cellular automata full-adder

In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Novel high-performance ternary circuits for nanotechnology are presented here. Each of these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the possible kinds of ternary logic, including negative, positive and standard ternary logics, in one structure. The proposed designs have good driving capability and large noise margins and are robust. These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes. This property of CNFETs makes them very suitable for the multiple- V t design method. The proposed circuits are simulated exhaustively, using Synopsys HSPICE with 32 nm-CNFET technology in various test situations and different supply voltages. Simulation results demonstrate great improvements in terms of speed, power consumption and insusceptibility to process variations with respect to other conventional and state-of-the-art 32 nm complementary metal-oxide semiconductor and CNFET-based ternary circuits. For instance at 0.9 V, the proposed ternary logic and arithmetic circuits consume on average 53 and 40 less energy, respectively, compared to the CNFET-based ternary logic and arithmetic circuits, recently proposed in the literature.

Design of energy-efficient and robust ternary circuits for nanotechnology

Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs

Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. In this paper we propose a novel 4x4 bit reversible multiplier circuit. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterparts. It is also better than the existing counterparts in term of number of gates, garbage outputs and constant inputs. Haghparast and Navi recently proposed a 4x4 reversible gate called "HNG". The reversible HNG gate can work singly as a reversible full adder. In this paper we use HNG gates to construct the reversible multiplier circuit. The proposed reversible multiplier circuit using HNG gate can multiply two 4-bits binary numbers. The proposed reversible 4x4 multiplier circuit can be generalized for NxN bit multiplication. We can use it to construct more complex systems in nanotechnology.

/pdf/design-of-a-novel-reversible-multiplier-circuit-using-hng-4na2isa0v0.pdf

Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology

Two new low-power Full Adders based on majority-not gates

This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple- V th circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2013.0023

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFET-based ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.

/pdf/efficient-cntfet-based-ternary-full-adder-cells-for-35f0q0w8yv.pdf

Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

This paper presents novel high-performance and PVT tolerant quaternary logic circuits as well as efficient quaternary arithmetic circuits for nanoelectronics. These Carbon Nanotube FET (CNFET)-based circuits are compatible with the recent technologies and are designed based on the conventional CMOS architecture, while the previous quaternary designs used methods which are not suitable for nanoelectronics and have become obsolete. The proposed designs are robust and have large noise margins and high driving capability. The singular characteristics of CNFETs, such as the capability of having the desired threshold voltage by regulating the diameters of the nanotubes, make them very appropriate for voltage-mode multiple-threshold circuits design. The proposed circuits are examined, using Synopsys HSPICE with the standard 32 nm-CNFET technology in various situations and different supply voltages. Simulation results demonstrate the correct and high-performance operation of the proposed circuits even in the presence of process, voltage and temperature variations.

Omid Hashemipour

Papers

Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology

Two new low-power Full Adders based on majority-not gates

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

Design and Evaluation of CNFET-Based Quaternary Circuits