The present invention provides OLEDs of the top emission type comprising organic light-emitting (LE) elements by preventing the problems such as the widening of the power lines, the reduction in the aperture ratio caused by the widening of the upper and the lower capacitor electrodes and the short circuit between the upper and the lower electrodes caused by the roughness of the flattening layers. Two kinds of the OLEDs are provided. One is an OLED comprising a region of LE layer sandwiched between the upper and lower electrodes is formed on a power line of TFT for driving the pixel. Another comprises a region of the LE layer formed on an electrode of capacitor connected to the TFTs to control the light-emitting element. Accordingly, without forming a flattening layer on the light-emitting layer, there is no electric short circuit between the lower electrode and the upper electrode.

Organic Light Emitting Display Device

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

Investigation of selective junctions using a newly developed tunnel current model for solar cell applications

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

A method of fabricating light-sensing devices including photodiodes monolithically integrated with CMOS devices. Several types of photodiode devices (PIN, HIP) are epitaxially grown in one single step on active areas implanted in a common semiconductor substrate, the active areas having defined polarities. The epitaxially grown layers for the photodiode devices may be either undoped or in-situ doped with profiles suitable for their respective operation. With appropriate choice of substrate materials, device layers and heterojunction engineering and process architecture, it is possible to fabricate silicon­based and germanium-based multi-spectral sensors that can deliver pixel density and cost of fabrication comparable to the state of the art CCDs and CMOS image sensors. The method can be implemented with epitaxially deposited films on the following substrates: Silicon Bulk, Thick-Film and Thin-Film Silicon-On-Insulator (SOI), Germanium Bulk, Thick-Film and Thin-Film Germanium-On-Insulator (GeOI).

Light-sensing device

A new photodiode for the UV/blue spectral range, which can be integrated monolithically with CMOS circuits, is presented. Such optoelectronic integrated circuits (OEICs) with a high sensitivity in the UV/blue spectral range are needed in near-future optical storage systems like digital versatile disk (DVD) or digital video recording (DVR). At 400 nm, our so-called finger photodiode achieves a responsivity of 0.23 A/W corresponding to a quantum efficiency /spl eta/ of 70% [with an antireflection coating (ARC)] and rise and fall times of 1.0 ns and 1.1 ns, respectively. The finger photodiode can be used in the red spectral range, too. At 638 nm, the responsivity is 0.49 A/W (/spl eta/=95%) and rise and fall times of less than 2.3 ns are achieved. For the integration of the finger photodiode in an industrial 1 /spl mu/m twin-well CMOS process, only one additional mask is needed in order to block out the threshold voltage implantation in the photo-active region.

CMOS photodiode with enhanced responsivity for the UV/blue spectral range

Results of a large-area, low-capacitance lateral p-i-n photodiode in silicon-on-insulator (SOI) are presented. This photodiode possesses an antireflection coating optimized for blue light and is therefore appropriate for scintillation detector applications. An average external quantum efficiency of 78.6% and 68.4% is achieved for /spl lambda/=430 nm and 400 nm, respectively. The rise and fall times of the lateral p-i-n photodiode for light with a wavelength of 400 nm are 9.7 ns and 11.2 ns, respectively. The capacitance of the SOI p-i-n photodiode is 0.72 pF/mm/sup 2/. This photodiode combines a high quantum efficiency and a low capacitance with a high speed.

Large-area lateral p-i-n photodiode on SOI

A new BiCMOS OEIC for advanced optical storage systems with enhanced bandwidths is presented. The photodiode and the amplifier are monolithically integrated on the same substrate of a standard BiCMOS process. The OEIC has a -3 dB-bandwidth of 147 MHz. Furthermore a monolithically integrated pin-photoreceiver in CMOS-technology capable of 622 Mbit/s at a single power supply of only 2.5V is introduced.

http://ieeexplore.ieee.org/iel5/9918/31527/01471180.pdf

Advanced CMOS and BiCMOS photonic receiver ICs

A problem of oxide non-uniformity in MOS tunnel structures on n-type Si with a 2–3 nm nominal SiO2 thickness dn is investigated. Thickness distribution is described with Gauss law. Concepts of modeling of reverse current–voltage characteristics are formulated for metal-oxide-semiconductor (MOS) tunnel structures, regarding the effect of non-uniformity. The current crowding in relatively thin device sections is shown to result in a noticeable transformation of curves for electron and hole tunnel currents. Introduction of a mean effective thickness deff instead of the nominal one is possible only for the weak-inversion regime. The experimental part of this work includes the examination of samples by TEM and atomic force microscope methods, and their electrical characterization. Measured characteristics have been satisfactorily fitted by curves simulated for a standard thickness deviation of σ=0.3 nm.

Current model considering oxide thickness non-uniformity in a MOS tunnel structure

New results for CMOS-OEICs (optoelectronic integrated circuits) suitable for optical data transmission and optical interconnects are presented. The integrated receivers achieve a data rate of 622 Mbit/s with a single power supply of 3.3 V.

P. Seegebrecht

Papers

CMOS photodiode with enhanced responsivity for the UV/blue spectral range

Large-area lateral p-i-n photodiode on SOI

Advanced CMOS and BiCMOS photonic receiver ICs

Current model considering oxide thickness non-uniformity in a MOS tunnel structure

Monolithic CMOS photoreceivers for short-range optical data communications