An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

With a global market share of about 90%, crystalline silicon is by far the most important photovoltaic technology today. This article reviews the dynamic field of crystalline silicon photovoltaics from a device-engineering perspective. First, it discusses key factors responsible for the success of the classic dopant-diffused silicon homojunction solar cell. Next it analyzes two archetypal high-efficiency device architectures – the interdigitated back-contact silicon cell and the silicon heterojunction cell – both of which have demonstrated power conversion efficiencies greater than 25%. Last, it gives an up-to-date summary of promising recent pathways for further efficiency improvements and cost reduction employing novel carrier-selective passivating contact schemes, as well as tandem multi-junction architectures, in particular those that combine silicon absorbers with organic–inorganic perovskite materials.

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High-efficiency crystalline silicon solar cells: status and perspectives

High-Performance Piezoelectric Energy Harvesters and Their Applications

In an effort to eliminate the replacement of the batteries of electronic devices that are difficult or impractical to service once deployed, harvesting energy from mechanical vibrations or impacts using piezoelectric materials has been researched over the last several decades. However, a majority of these applications have very low input frequencies. This presents a challenge for the researchers to optimize the energy output of piezoelectric energy harvesters, due to the relatively high elastic moduli of piezoelectric materials used to date. This paper reviews the current state of research on piezoelectric energy harvesting devices for low frequency (0–100 Hz) applications and the methods that have been developed to improve the power outputs of the piezoelectric energy harvesters. Various key aspects that contribute to the overall performance of a piezoelectric energy harvester are discussed, including geometries of the piezoelectric element, types of piezoelectric material used, techniques employed to match the resonance frequency of the piezoelectric element to input frequency of the host structure, and electronic circuits specifically designed for energy harvesters.

/pdf/energy-harvesting-from-low-frequency-applications-using-33u6ct9j73.pdf

Energy harvesting from low frequency applications using piezoelectric materials

A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Microelectronic packages and methods therefor

Electromigration induced damage strongly depends on Sn-grain orientation in Pb-free solders. Rapid depletion of intermetallic compounds and under bump metallurgy led to significant damages caused by the fast diffusion of Cu and Ni along the c axis of Sn crystals. When the c axis of Sn grain is not aligned with the current direction, electromigration (EM) damage is dominated by Sn self-diffusion, which takes longer to occur. This is a direct proof of the highly anisotropic diffusion behavior in Sn. Due to the presence of twin structures and stable Ag3Sn network, SnAg(Cu) solders are less susceptible to grain orientation effects and showed better EM performance than SnCu solders.

Effect of Sn grain orientation on electromigration degradation mechanism in high Sn-based Pb-free solders

The present invention is directed to a structure (2) for packaging electronic devices, such as semiconductor chips (36, 38), in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies (4, 6). Each assembly is formed from a substrate (8) having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection means (49) electrically interconnecting each assembly. The electrical interconnection means is formed from an elastomeric interposer. The elastomeric interposer is formed from an elastomeric material having a plurality of electrical conductors extending therethrough, either in a clustered or un-clustered arrangement. The electrical interconnection means is fabricated having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection means is disposed over the array of electronic devices so that the electrical interconnection means is between adjacent electronic devices. The stack of assemblies is compressed thereby compressing the electrical interconnection means between adjacent assemblies. The substrate of each assembly is formed from a thermally conductive material such as diamond. A heat dissipation means is thermally connected to the edges of the substrate to extract heat generated within the structure. Methods for fabricating the electrical interconnection means as a stand alone elastomeric sheet are described. The ends (50, 54) of the plurality of conductors in the electrical interconnection means (49) are fabricated so that upon compression between adjacent assemblies (4, 6) there is a wiping action between the conductor ends (e.g. 50) and contact locations (e.g. 30) on the adjacent assemblies to form a good electrical contact therewith.

Three dimensional high performance interconnection package

During the solidification of solder joints composed of near-eutectic Sn–Ag–Cu alloys, the Sn phase grows rapidly with a dendritic growth morphology, characterized by copious branching. Notwithstanding the complicated Sn growth topology, the Sn phase demonstrates single crystallographic orientations over large regions. Typical solder ball grid array joints, 900 μm in diameter, are composed of 1 to perhaps 12 different Sn crystallographic domains (Sn grains). When such solder joints are submitted to cyclic thermomechanical strains, the solder joint fatigue process is characterized by the recrystallization of the Sn phase in the higher deformation regions with the production of a much smaller grain size. Grain boundary sliding and diffusion in these recrystallized regions then leads to extensive grain boundary damage and results in fatigue crack initiation and growth along the recrystallized Sn grain boundaries.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S0884291400093729

The microstructure of Sn in near-eutectic Sn-Ag-Cu alloy solder joints and its role in thermomechanical fatigue

Probes for electronic devices are described. The probe is formed by ball bonding a plurality of wires to contact locations on a fan out substrate surface. The wires are cut off leaving stubs. A patterned polymer sheet having electrical conductor patterns therein is disposed over the stubs which extend through holes in the sheet. The ends of the wires are flattened to remit the polymer sheet in place. The wire is connected to an electrical conductor on the polymer sheet which is converted to a contact pad on the polymer sheet. A second wire is ball bonded to the pad on the polymer sheet and cut to leave a second stub. The polymer sheet is laser cut so that each second stub is free to move independently of the other second studs. The ends of the second stubs are disposed against contact locations of an electronic device, such as an FC chip, to test the electronic device.

High density cantilevered probe for electronic devices

The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

Paul A. Lauro

Papers

Effect of Sn grain orientation on electromigration degradation mechanism in high Sn-based Pb-free solders

Three dimensional high performance interconnection package

The microstructure of Sn in near-eutectic Sn-Ag-Cu alloy solder joints and its role in thermomechanical fatigue

High density cantilevered probe for electronic devices

High density integrated circuit apparatus, test probe and methods of use thereof