Showing papers by "Paul Jespers published in 1994"

A 10-bit pipelined switched-current A/D converter

Abstract: A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm/sup 2/. The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy. >

Comparison of SOI versus bulk performances of CMOS micropower single-stage OTAs

Abstract: The performances of micropower single-stage CMOS OTAs implemented in SOI or bulk technologies are compared. The improvements resulting from the superior device characteristics of fully-depleted SOI MOSFETs are discussed. Experimental verifications support the theoretical predictions.

Design of thin-film fully-depleted SOI CMOS analog circuits significantly outperforming bulk implementations

Abstract: Although the reduction of parasitic capacitance and the feasibility of diffusion resistors and capacitors free of junction effects have long been recognized as advantages for the realization of analog circuits on SOI substrates, few SOI analog circuits have been reported mainly because the kink effect severely degrades the output characteristics of thick-film SOI MOSFETs and thereby the performances of analog circuits. Operational amplifier solutions such as the use of body contacts, twin-gate devices or gain-boosting have been proposed but offer little improvement over bulk CMOS counterparts, with the exception of the resistance to elevated temperatures. In the present paper we propose new design models and techniques which, by exploiting the smaller subthreshold swing and body factor of thin-film fully-depleted (FD) SOI MOSFETs, could provide a major breakthrough in order to boost the performances of SOI CMOS analog circuits substantially over bulk implementations, especially in the field of low-voltage low-power applications.

A micropower switched capacitor implementation of the silicon cochlea

Abstract: This paper presents the implementation in micropower technique of a switched capacitor (SC) silicon cochlea. Its main features are: very low power consumption, enhanced behaviour compared to previous realizations and a true integrability inside a real hearing prosthesis. The silicon cochlea is based on a cascade of 40 programmable SC second order low-pass filters and achieves a power consumption of less than 100 ?W with a supply of 3V and a sampling frequency (Fs = 1/T) of 200 KHz.