In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

A comprehensive survey of thinning methodologies is presented. A wide range of thinning algorithms, including iterative deletion of pixels and nonpixel-based methods, is covered. Skeletonization algorithms based on medial axis and other distance transforms are not considered. An overview of the iterative thinning process and the pixel-deletion criteria needed to preserve the connectivity of the image pattern is given first. Thinning algorithms are then considered in terms of these criteria and their modes of operation. Nonpixel-based methods that usually produce a center line of the pattern directly in one pass without examining all the individual pixels are discussed. The algorithms are considered in great detail and scope, and the relationships among them are explored. >

Thinning methodologies-a comprehensive survey

A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.

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A reliable approach to charge-pumping measurements in MOS transistors

A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

Measurements of intrinsic gate capacitances of SOI MOSFETs are described and are shown to provide valuable information for characterizaton purposes as well as to cast some light on dynamic floating substrate effects. An accurate charge-based analytical model valid in linear operation is also presented.

Intrinsic gate capacitances of SOI MOSFETs: measurement, modelling, floating substrate effects

This paper describes a method to model thin-film fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs at frequencies where the quasi-static model is no longer valid The method consists in considering a cascade of several elementary MOSFET transistors or sections and applying the quasi-static analysis to each section Important second-order effects such as mobility degradation and velocity saturation are considered in each individual section Two different approaches to choose the dimensions of each section are analyzed This technique is compared to a complete quasi-static analysis and results are discussed Also, scattering parameters measurements are presented

A method to extend the validity of quasi-static SOI MOSFET models

In Chapter 1, the Intrinsic Gain Stage was sized in strong and weak inversion and, in Chapter 4, in moderate inversion. Only gradual channel models were utilized. The extension of the E.K.V model to short channel devices considered in Chapter 5 paves the way towards the sizing of real Intrinsic Gain Stages.

The Real Intrinsic Gain Stage

The total area of the active circuit is 400 urn X 225 #m without layout optimization. An optimum design using the same layout rules and parallel collector structures would result in an area of about 270 pm X 90 #m. The corresponding area for a binary 12L full adder fabricated using the same technology and layout rules and perpendicular collector structures was crdculated to be 290 m X 120 pm. This implies that an opY timized multivalued I L full adder circuit occupies 70 percent of the area of the binary full adder. If the multivrdued 12L full adder is constructed usihg perpendicular collector structures, a further reduction in area would result. The 12L threshold gates were characterized by measuring 6P and &. A curve tracer was used for the measurements. The typical value of PMwas 3 for collector currents ranging from 20 to 200 PA. In the same range of currents, thle value of & was 600. The beta matching for a set of three collectors in a parallel structure with a unity area injector was found to be better than 3 percent over a range of current from 10 pA to 1 mA. The collector-to-emitter breakdown voltage for the upside-down n-p-n transistor was 1.6 V. The full adder operation was successfully tested at low frequency using three synchronized input signals applied to terminals Xl , X2, and Cl. A TTL-to-12 L interface consisting of a single inverter stage was used at the input and an 12L-toTTL interface consisting of two inverters in series was used at the output. The speed of operation of the circuit was tested with a stable dc level corresponding to a “one” at the Xl input, a stable dc level corresponding to a “zero” at the X2 input, and a pulse applied to the Cl input. The delays of the sum and carry outputs are t~~= 1.5 ps and tjc= 0.9 ps, respectively, at an injector current of 75 IA. These delays include the delays of the input and output interfaces. The intrinsic values of the delays without the interfaces are td$ = 1.2 us and td~= 0.6 #s. In the multilevel full adder, all three inputs are interchangeable and the resultant delay is the same for any combination of a dc “zero” input, a dc “one” input, and a pulsed input. For compwison purposes, the corresponding intrinsic sum delay for a binary full adder operated at the same injection current and using the same interfaces was found to be approximately 0.8 p.s. In the case of thle binary full adder, all three inputs are not directly interchangeable and the delay depends on whether one of the inputs o.r the carry is clocked. The value 0.8 ps for the delay was obtained by averaging the delays for the case of a dc “zero” input, a dc “one” input, and a clocked carry and the case of a dc “zero” input, a clocked input, and a dc “one” carry. Therefore, it appears that for the same power dissipation, the area x delay product (in this case the delay refers to the delay associated with the sum output) for the multivalued full adder is approximately the same as for the binary full adder. CONCLUSION The multivalued full adder implemented using 12 L technology offers a sizable reduction in area while operating at approximately the same area x delay product as the binary version. The logic scheme described in this correspondence can be applied to the realization of a variety of other logic functions and, furthermore, (can be extended to levels higher than four with improvements in processing technology.

Cell Three-Terminal CID as Random Access Memory

Redundancy in the output code, as instrument to reduce the impact of non-idealities in different architectures of two-step A to D converters, is investigated. A circuit model capable of providing an estimate of the required sizes for passive components for a given accuracy was developed. Such model represents an useful design tool, providing a way to calculate important figures of merit (area, power, ENOB, SNR, large-signal behavior) of the different ADCs. System-level simulation results are provided and discussed.

Paul Jespers

Papers

Intrinsic gate capacitances of SOI MOSFETs: measurement, modelling, floating substrate effects

A method to extend the validity of quasi-static SOI MOSFET models

The Real Intrinsic Gain Stage

Cell Three-Terminal CID as Random Access Memory

Comparison of redundant architectures for two-step ADCs