In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

A comprehensive survey of thinning methodologies is presented. A wide range of thinning algorithms, including iterative deletion of pixels and nonpixel-based methods, is covered. Skeletonization algorithms based on medial axis and other distance transforms are not considered. An overview of the iterative thinning process and the pixel-deletion criteria needed to preserve the connectivity of the image pattern is given first. Thinning algorithms are then considered in terms of these criteria and their modes of operation. Nonpixel-based methods that usually produce a center line of the pattern directly in one pass without examining all the individual pixels are discussed. The algorithms are considered in great detail and scope, and the relationships among them are explored. >

Thinning methodologies-a comprehensive survey

A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.

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A reliable approach to charge-pumping measurements in MOS transistors

A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

Process and Device Modeling for Integrated Circuit Design

The purpose of the circuit presented was to test the implementation of dynamically refreshed analog memories using conventional CMOS technology with special care in achieving high resolution with small silicon area, and small read-write access time. The circuit prototype implements adjustable analog synaptic weights, compatible with an analog multiplier. The synaptic weights are dynamically refreshed with an on-chip system based on A/D and D/A conversion. The circuit has been fully tested, and a resolution of 7 bits per memory cell was measured. These are arranged in an array of 14*15 cells. A Kohonen neural network with on-chip learning system, which is based on this analog memory implementation is presented. The form of the `Mexican hat' and learning rate are digitally adjustable. No multipliers are required for this implementation, only differences are calculated. This circuit is under design.

Analog storage of adjustable synaptic weights

Although the reduction of parasitic capacitance and the feasibility of diffusion resistors and capacitors free of junction effects have long been recognized as advantages for the realization of analog circuits on SOI substrates, few SOI analog circuits have been reported mainly because the kink effect severely degrades the output characteristics of thick-film SOI MOSFETs and thereby the performances of analog circuits. Operational amplifier solutions such as the use of body contacts, twin-gate devices or gain-boosting have been proposed but offer little improvement over bulk CMOS counterparts, with the exception of the resistance to elevated temperatures. In the present paper we propose new design models and techniques which, by exploiting the smaller subthreshold swing and body factor of thin-film fully-depleted (FD) SOI MOSFETs, could provide a major breakthrough in order to boost the performances of SOI CMOS analog circuits substantially over bulk implementations, especially in the field of low-voltage low-power applications.

Design of thin-film fully-depleted SOI CMOS analog circuits significantly outperforming bulk implementations

A novel circuit performing the division operation is proposed. The numerator and denominator input data are currents whereas thr output quotient is a voltage. The circuit was designed to bs used in the defuzzifier of a fuzzy controller.

Two-quadrant CMOS analogue divider

SOI technology offers significant assets for low-voltage, low-power high-speed logic. The steeper subthreshold slope of SOI MOSFETs not only improves design of low-voltage logic circuits, but also offers also opportunities for low-power analog design. Identical DC gains can be achieved in SOI and bulk either with less current or smaller geometries, or both. This is illustrated by plots of total area and stand-by current versus DC open-loop gain of two identical Miller op amps, one bulk and one SOI.

Paul Jespers

Papers

Process and Device Modeling for Integrated Circuit Design

Analog storage of adjustable synaptic weights

Design of thin-film fully-depleted SOI CMOS analog circuits significantly outperforming bulk implementations

Two-quadrant CMOS analogue divider

Potential of SOI for analog and mixed analog-digital low-power applications