Showing papers by "Paul S. Ho published in 2014"

Thermomechanical Failure Analysis of Through-Silicon Via Interface Using a Shear-Lag Model With Cohesive Zone

Abstract: An analytical approach to predict initiation and growth of interfacial delamination in the through-silicon via structure is developed by combining a cohesive zone model with a shear-lag model. Two critical temperatures are predicted for damage initiation and fracture initiation, respectively. It is found that via extrusion significantly increases beyond the second critical temperature. The dependence of the critical temperatures on the material/interfacial properties, as well as the via size (diameter and height), is discussed. In parallel with the analytical approach, finite-element models with cohesive interface elements are employed to numerically simulate the initiation and the progression of interfacial delamination. The numerical results are in good agreement with the analytical solution, and both are qualitatively consistent with reported experimental findings by others.

Study of Stresses and Plasticity in Through-Silicon Via Structures for 3D Interconnects by X-Ray Micro-Beam Diffraction

Abstract: X-ray microbeam diffraction measurements were conducted for copper (Cu) through-silicon via (TSV) structures. This technique has the unique capability to measure stress and deformation in Cu and in silicon with submicron resolution, which enables direct observation of the local plasticity in Cu and the deformation induced by thermal stresses in TSV structures. Grain growth in Cu vias was found to play an important role in controlling the stress relaxation during thermal cycling and, thus, the residual stress and plasticity in the TSV structure. The implication of the local plasticity on TSV reliability is discussed based on the results from this study and finite element analysis.

Impact of Grain Structure and Material Properties on Via Extrusion in 3D Interconnects

Abstract: In this article, the effects of Cu microstructure on the mechanical properties and extrusion of through-silicon vias (TSVs) were studied based on two types of TSVs with different microstructure. A direct correlation was found between the grain size and the mechanical properties of the vias. Both an analytical model and finite element analysis (FEA) were used to establish the relationship between the mechanical properties and via extrusion. The effect of via/Si interface on extrusion was also studied by FEA. The results suggest small and uniform grains in the Cu vias, as well as stronger interfaces between the via and Si led to smaller via extrusion, and are thus preferable for reduced via extrusion failure and improved TSV reliability.

Scaling effects on microstructure and electromigration reliability for Cu and Cu(Mn) interconnects

Abstract: EM reliability of Cu and Cu(Mn) interconnects was investigated, focusing on the scaling effect on grain structure and mass transport. The microstructure of Cu and Cu(Mn) interconnects was characterized up to the 22 nm node using a high-resolution TEM diffraction technique. Compared to Cu interconnects of the 45 nm node, the 28 nm Cu(Mn) structures were found to have a strong {111} texture along the line length direction and a low fraction of coherent twin boundaries (~2%). Inclusion of Mn was found to be important for microstructure evolution. The effect of Mn alloying on EM reliability was examined by comparing the lifetime statistics to Cu interconnects with standard SiCN cap and CoWP metal cap. The interfacial and GB diffusivities together with activation energies were extracted from resistance traces in EM tests. Mn was found to effectively reduce EM-induced mass transport, particularly for interfacial diffusion. These results were combined to project the Mn alloying effect for future technology.

Material characterization and failure analysis of through-silicon vias

Abstract: In this paper, the effects of Cu microstructure on the mechanical properties of TSV and via extrusion are studied using two types of through-silicon vias (TSVs) with different grain size distributions. A direct correlation is found between the Cu grain size and the mechanical properties of the TSVs. An analytical model is used to explore the relationship between the mechanical properties and via extrusion. The results show that small and uniform grains in the Cu vias led to smaller via extrusion. Such grain structures are effective for reducing via extrusion failure to improve TSV reliability.

Effect of high temperature storage on the stress and reliability of 3D stacked chip

Abstract: In this work, the effect of high temperature storage (HTS) on the stress in and around Cu TSVs in 3D stacked chips is studied by scanning white beam x-ray microdiffraction. The x-ray microdiffraction measurements were conducted on different die levels in the stacked chips before and after HTS test. High resolution mappings of stress distribution were obtained and compared between pre-HTS and post-HTS for both the Cu via and the surrounding Si. The x-ray microdiffraction technique provides a means for nondestructive, direct stress measurement in a 3D die stack structure. Finite element analysis (FEA) was carried out for the test structure to interpret the measurement results and to discuss the thermal aging effect on the 3D chip. Overall, the results show reduced stress in both Cu and Si after HTS, which can be explained by stress relaxation occurred during HTS. The implication of the HTS results on long term reliability of 3D die stacks is discussed.

Effect of microstructure on via extrusion profile and reliability implication for copper through-silicon vias (TSVs) structures

Abstract: In this work, the effect of grain structure on TSV extrusion and its reliability implication are investigated through experimental measurements and modeling analysis. The grain orientation, elastic anisotropy and local plasticity are found to be important in controlling the extrusion profile which can directly impact the back-end-of-line (BEOL) reliability. Results from this study suggest that the Cu microstructure should be optimized from both global and local aspects in order to minimize the extrusion damage to the 3D structure.

Self-aligned masks and methods of use

Abstract: The disclosure relates to a method for forming a nanoscale structure by forming a pattern on a selectively etched layer located on top of a substrate using lithography, wherein the pattern results a gap having sidewalls, performing RIE on the gap having sidewalls, wherein RIE results in the formation of a self-aligned mask on the bottom wall of the gap with unprotected regions on the bottom wall of the gap near the junctions with the sidewalls, and wet etching the gap having a self-aligned mask and unprotected regions to remove the substrate under the unprotected regions to form a nanoscale structure in the substrate. The disclosure also relates to a nanoscale structure array including a plurality of nanotrenches, nanochannels or nanofins having a width of 50 nm or less and an average variation in width of 5% or less along the entire length of each nanotrench, nanochannel or nanofin.

Characterization of thermal stresses and plasticity in through-silicon via structures for three-dimensional integration

Abstract: Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) integration. The mismatch of thermal expansion coefficients between the Cu via and Si can generate significant stresses in the TSV structure to cause reliability problems. In this study, the thermal stress in the TSV structure was measured by the wafer curvature method and its unique stress characteristics were compared to that of a Cu thin film structure. The thermo-mechanical characteristics of the Cu TSV structure were correlated to microstructure evolution during thermal cycling and the local plasticity in Cu in a triaxial stress state. These findings were confirmed by microstructure analysis of the Cu vias and finite element analysis (FEA) of the stress characteristics. In addition, the local plasticity and deformation in and around individual TSVs were measured by synchrotron x-ray microdiffraction to supplement the wafer curvature measurements. The importance and implication of the local plasticity and residual stress on TSV reliabilities are discussed for TSV extrusion and device keep-out zone (KOZ).

Methods of fabricating silicon nanowires and devices containing silicon nanowires

Abstract: The present disclosure relates to a method of fabricating a silicon nanowire having a width of 100 nm or less, especially 50 nm or less, by depositing a metal film on a silicon-containing layer, treating the metal film using a wet process to produce an interconnected metal network having gaps on the silicon-containing layer, and etching the silicon-containing layer with a metal-assisted etching process to form a silicon nanowire having a width of 100 nm or less, especially 50 nm or less. The present disclosure also relates to lithium ion batteries, thermoelectric materials, solar cells, chemical and biological sensors, and drug delivery devices containing silicon nanowires.

A kinetic decomposition process for air-gap interconnects and induced deformation instability of a low-k dielectric cap layer

Abstract: During air-gap formation in interconnects, decomposition process of the sacrificial layer induces deformation of a low-k dielectric cap layer. For analysis of ensuing structural instability, a logistic kinetics model is introduced to describe the removal process of the sacrificial layer, and finite difference method (FDM) is applied to evaluate the deformation behavior of the cap layer. The instability of the cap layer depends on its span length and the degree of adhesion between the cap layer and sacrificial layer. During decomposition, strong adhesion causes the collapse of the cap layer, while the cap deformation remains small and stable with weak adhesion. For intermediate adhesion, a snap-back instability is predicted as the cap layer suddenly detaches from the sacrificial layer at a critical deflection. The critical adhesion energy is predicted as a function of the air gap width.

Thermomechanical characterization and modeling for TSV structures

Abstract: Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future technology requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper presents experimental measurements of the thermal stresses in TSV structures and analyses of interfacial reliability. The micro-Raman measurements were made to characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the precision wafer curvature technique was employed to measure the average stress and deformation in the TSV structures subject to thermal cycling. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias was analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. Furthermore, the impact of thermal stresses on interfacial reliability of TSV structures was investigated by a shear-lag cohesive zone model that predicts the critical temperatures and critical via diameters.