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Thomas Ernst
Researcher at University of Grenoble
Publications - 183
Citations - 4154
Thomas Ernst is an academic researcher from University of Grenoble. The author has contributed to research in topics: MOSFET & Electron mobility. The author has an hindex of 33, co-authored 181 publications receiving 3925 citations. Previous affiliations of Thomas Ernst include Alternatives & Centre national de la recherche scientifique.
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Proceedings ArticleDOI
A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration
Arnaud Hubert,Etienne Nowak,K. Tachi,V. Maffini-Alvaro,C. Vizioz,Christian Arvet,J. P. Colonna,J.M. Hartmann,Virginie Loup,L. Baud,S. Pauliac,Vincent Delaye,C. Carabasse,G. Molas,Gerard Ghibaudo,B. De Salvo,O. Faynot,Thomas Ernst +17 more
TL;DR: In this article, the Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter) is extended to an independent double gate memory architecture, called φ-Flash.
Journal ArticleDOI
Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm
Sylvain Barraud,Matthieu Berthomé,R. Coquand,Mikael Casse,Thomas Ernst,Marie-Pierre Samson,P. Perreau,Konstantin Bourdelle,Olivier Faynot,Thierry Poiroux +9 more
TL;DR: In this article, the performance of high-κ /metal gate nanowire (NW) transistors without junctions is reported, with a channel thickness of 9 nm and sub-15-nm gate length and width.
Journal ArticleDOI
Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs
TL;DR: In this article, the feasibility of split capacitance-voltage measurements in sub-0.1 /spl mu/m Si MOSFETs is demonstrated, and an improved methodology to extract accurately the effective channel length and the effective mobility is proposed.
Proceedings ArticleDOI
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
O. Faynot,Francois Andrieu,Olivier Weber,Claire Fenouillet-Beranger,Pierre Perreau,J. Mazurier,T. Benoist,O. Rozeau,Thierry Poiroux,Maud Vinet,Laurent Grenouillet,J.-P. Noel,Nicolas Posseme,Sébastien Barnola,François Martin,C. Lapeyre,Mikael Casse,X. Garros,M-A. Jaud,Olivier P. Thomas,G. Cibrario,L. Tosti,L. Brevard,Claude Tabone,P. Gaud,Sylvain Barraud,Thomas Ernst,Simon Deleonibus +27 more
TL;DR: In this article, the main advantages of planar undoped channel Fully depleted SOI devices are discussed and solutions to the Multiple V T challenges and non logic devices (ESD, I/Os) are reported.
Journal ArticleDOI
Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture
TL;DR: In this article, a compact model of the lateral field penetration in the buried oxide (BOX) and underlying substrate of fully depleted SOI MOSFETs is proposed and used to explore optimized architectures of sub-100 nm transistors.