This paper presents a comprehensive full-scale three-dimensional simulation scaling study of the statistical threshold-voltage variability in bulk high-k/metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granularity (MGG) and corresponding workfunction-induced threshold-voltage variability have become important sources of statistical variability in bulk HKMG MOSFETs. It is found that the number of metal grains covering the gate plays an important role in determining the shape of the threshold-voltage distribution and the magnitude of the threshold-voltage variability in scaled devices in the presence of dominant variability sources (MGG, random discrete dopants, and line edge roughness). The placement of metal grains is found to also contribute to the total MGG variability. This paper presents the relative importance of MGG compared with other statistical variability sources. It is found that MGG can distort and even dominate the threshold-voltage statistical distribution when the metal grain size cannot be adequately controlled.

Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study

Forthcoming technology nodes are posing major challenges on the manufacturing of reliable (real-time) systems: process variations, accelerated degradation aging, as well as external and internal noise are key examples This paper focuses on real-time systems reliability and analyzes the state-of-the-art and the emerging reliability bottlenecks from three different perspectives: technology, circuit/IP and full system

http://ce-publications.et.tudelft.nl/publications/1411_reliability_challenges_of_realtime_systems_in_forthcoming.pdf

Reliability challenges of real-time systems in forthcoming technology nodes

Simulations of up to 10 000 fully depleted thin-body silicon-on-insulator MOSFETs show that the standard deviation of the threshold voltage cannot be adequately used as a sole metric of device variability in such transistors. This is due to a sharp departure from normality of the threshold voltage distribution, and an enhanced influence of the source/drain-dopant fluctuations on the on-current and short-channel effects of the fully depleted thin-body silicon-on-insulator transistors. Both aspects have great ramifications for statistical compact models and for low-power SRAM designs.

Statistical Variability in Fully Depleted SOI MOSFETs Due to Random Dopant Fluctuations in the Source and Drain Extensions

Despite a number of recent advances made in understanding bias temperature instability (BTI), there is still no simple simulation methodology available which can capture the impact of BTI degradation on deeply scaled transistors, while incorporating the widely distributed defect parameters. We present a physics-based defect-controlled methodology for projecting defect property distributions into circuit lifetime and performance distributions. This methodology allows evaluating the entire population of traps (from fast to slow recoverable and permanent traps), which results in faster simulation and proper extrapolation towards long operating lifetimes.

Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM

This paper describes the implications of bias temperature instability (BTI)-induced time-dependent threshold voltage distributions on the performance and yield estimation of digital circuits. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The impact of using normally distributed threshold voltages, imposed by state-of-the-art design approaches, is contrasted with our defect-centric approach. Extensive Monte Carlo simulation results are shown for static random access memory cell and ring oscillator structures.

Implications of BTI-Induced Time-Dependent Statistics on Yield Estimation of Digital Circuits

Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. Most problematic of all is the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions [i]. Two transistors next to each other on the chip with exactly the same geometries and strain distributions may have characteristics from each end of a wide statistical distribution. In conjunction with statistical variability [ii], negative bias temperature instability (NBTI) and/or hot carrier degradation can result in acute statistical reliability problems. It already profoundly affects SRAM design, and in logic circuits causes statistical timing problems and is increasingly leading to hard digital faults. In both cases, statistical variability restricts supply voltage scaling, adding to power dissipation problems [iii]. In this invited paper we describe recent advances in predictive physical simulation of statistical variability using drift diffusion (DD), Monte Carlo (MC) and quantum transport (QT) simulation techniques.

http://userweb.eng.gla.ac.uk/andrew.brown/papers/IEDM_2008.pdf

R.A. Brown

Papers

Advanced simulation of statistical variability and reliability in nano CMOS transistors