Solid-state electronics

A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.

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Statistical variability and reliability in nanoscale FinFETs

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

Since Moore’s law driven scaling of planar MOSFETs
faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing
to the presence of multiple (two/three) gates, FinFETs/Trigate
FETs are able to tackle short-channel effects (SCEs) better than
conventional planar MOSFETs at deeply scaled technology nodes
and thus enable continued transistor scaling. In this paper, we
review research on FinFETs from the bottommost device level
to the topmost architecture level. We survey different types of
FinFETs, various possible FinFET asymmetries and their impact,
and novel logic-level and architecture-level tradeoffs offered by
FinFETs. We also review analysis and optimization tools that
are available for characterizing FinFET devices, circuits, and
architectures.

/pdf/finfets-from-devices-to-architectures-3wvjf3zgcz.pdf

FinFETs: From Devices to Architectures

Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7- and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 〈110〉 channel orientation is more resilient to the MGG and LER variability in both architectures.

/pdf/finfet-versus-gate-all-around-nanowire-fet-performance-2wdmnm8wlp.pdf

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

This paper presents a comprehensive full-scale three-dimensional simulation scaling study of the statistical threshold-voltage variability in bulk high-k/metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granularity (MGG) and corresponding workfunction-induced threshold-voltage variability have become important sources of statistical variability in bulk HKMG MOSFETs. It is found that the number of metal grains covering the gate plays an important role in determining the shape of the threshold-voltage distribution and the magnitude of the threshold-voltage variability in scaled devices in the presence of dominant variability sources (MGG, random discrete dopants, and line edge roughness). The placement of metal grains is found to also contribute to the total MGG variability. This paper presents the relative importance of MGG compared with other statistical variability sources. It is found that MGG can distort and even dominate the threshold-voltage statistical distribution when the metal grain size cannot be adequately controlled.

Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study

The strategy to generate statistical model parameters is essential for variability-aware design. Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models.

Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

Through oxygen profile engineering, we fabricated W/AlO $_{\mathbf {x}}$ /Al $_{\mathbf {{2}}}~\text{O}_{\mathbf {{3}}}$ /Pt bilayer memristors with a 250-nm feature size. The AlO $_{{\mathbf {x}}}$ fabricated by sputtering serves as an oxygen vacancy source, whereas the Al $_{{\mathbf {{2}}}}~\text{O}_{{\mathbf {{3}}}}$ deposited by atomic layer deposition acts as a dominant resistive switching (RS) layer. Our devices show forming-free RS behaviors with high speed (28 ns), uniform resistance distribution, large on/off ratio ( $\sim 10^{{\mathbf {{3}}}}$ @100K, $\sim 10^{{\mathbf {{3}}}}$ @298K, and $\sim 80$ @400K), and good retention. Besides, temperature stability with record high endurance from cryogenic to high-temperature ( $10^{{\mathbf {{8}}}}$ @100K, $10^{{\mathbf {{10}}}}$ @298K, and $10^{{\mathbf {{7}}}}$ @400K) is demonstrated, to the best of our knowledge.

Forming-Free, Fast, Uniform, and High Endurance Resistive Switching From Cryogenic to High Temperatures in W/AlO x /Al 2 O 3 /Pt Bilayer Memristor

Comprehensive 3-D simulations have been carried out and compared with experimental data highlighting the dominant sources of statistical variability in 32-nm high-κ/metal gate MOSFET technology. The statistical variability sources include random discrete dopants, line edge roughness, and metal gate granularity. Their relative importance is highlighted in the numerical simulations. Excellent agreement is achieved between the simulated and measured standard deviation of the threshold voltage.

Xingsheng Wang

Papers

Statistical variability and reliability in nanoscale FinFETs

Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study

Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

Forming-Free, Fast, Uniform, and High Endurance Resistive Switching From Cryogenic to High Temperatures in W/AlO x /Al 2 O 3 /Pt Bilayer Memristor

Simulation Study of Dominant Statistical Variability Sources in 32-nm High- $\kappa$ /Metal Gate CMOS