https://www.cse.iitk.ac.in/users/isaha/Publications/Journals/NC10.pdf/

Artificial neural networks in hardware: A survey of two decades of progress

Solid-state electronics

https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

(IEEE Transactions on Electron Devices,36(12):2816-2820)Field-Drifting Resonant Tunneling Through a-Si:H/a-Sil-xCx:H Quantum Wells at Different Locations of the i-Layer of a p-i-n Structure

In this paper, using three-dimensional statistical numerical simulations, the authors study the intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness (LER), and oxide-thickness variations in realistic bulk MOSFETs scaled to 25, 18, 13 and 9 nm. The scaling is based on a 35 nm MOSFET developed by Toshiba, which has also been used for the calibration of the authors' "atomistic" device simulator. Special attention is paid to the accurate resolution of the individual discrete dopants in the drift-diffusion simulations by introducing density-gradient quantum corrections for both electrons and holes. In the LER simulations, two scenarios have been adopted: in the first one, LER follows the prescriptions of the International Roadmap for Semiconductors; in the second one, LER is kept constant close to the current best values. Combined effects of the different sources of intrinsic parameter fluctuations have also been simulated in the 35 nm reference devices and the results for the standard deviation of the threshold voltage compared to the measured values

http://userweb.eng.gla.ac.uk/andrew.brown/papers/IEEE_TED_2006_Scaled_Devices.pdf

Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs

A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.

/pdf/statistical-variability-and-reliability-in-nanoscale-finfets-2xa0999wwu.pdf

Statistical variability and reliability in nanoscale FinFETs

An ‘atomistic’ circuit simulation methodology is developed to investigate intrinsic parameter fluctuations introduced by discreteness of charge and matter in decananometer scale MOSFET circuits. Based on the ‘real’ doping profile, the impact of random device doping on 6-T SRAM static noise margins are discussed in detail for 35 nm physical gate length devices. We conclude that SRAM may not gain all the benefits of future bulk CMOS scaling, and new device architectures are needed to scale SRAM down to future technology node.

Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells

A quantitative evaluation of the contributions of different sources of statistical variability, including the contribution from the polysilicon gate, is provided for a low-power bulk N-MOSFET corresponding to the 45-nm technology generation. This is based on a joint study including both experimental measurements and ldquoatomisticrdquo simulations on the same fully calibrated device. The position of the Fermi-level pinning in the polysilicon bandgap that takes place along grain boundaries was evaluated, and polysilicon-gate-granularity contribution was compared to the contributions of other variability sources. The simulation results indicate that random discrete dopants are still the dominant intrinsic source of statistical variability, while the role of polysilicon-gate granularity is highly dependent on Fermi-level pinning position and, consequently, on the structure of the polysilicon-gate material and its deposition and annealing conditions.

http://userweb.eng.gla.ac.uk/andrew.brown/papers/IEEE_EDL_2008_45nm.pdf

Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET

The strategy to generate statistical model parameters is essential for variability-aware design. Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models.

Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

In this paper, we present models and tools developed and used by the Device Modelling Group at the University of Glasgow to study statistical variability introduced by the discreteness of charge and matter in contemporary and future Nano-CMOS transistors. The models and tools, based on Drift-Diffusion (DD), Monte Carlo (MC) and Non-Equilibrium Green’s Function (NEGF) techniques, are encapsulated in the Glasgow 3D statistical ‘atomistic’ device simulator. The simulator can handle most of the known sources of statistical variability including Random Discrete Dopants (RDD), Line Edge Roughness (LER), Thickness Fluctuations in the Oxide (OTF) and Body (BTF), granularity of the Poly-Silicon (PSG), Metal Gate (MGG) and High-κ (HKG), and oxide trapped charges (OTC). The results of the statistical simulations are verified with respect to measurements carried out on fabricated devices. Predictions about the magnitude of the statistical variability in future generations of nano-CMOS devices are also presented.

Binjie Cheng

Papers

Statistical variability and reliability in nanoscale FinFETs

Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells

Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET

Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Green’s function techniques