R. Barth

TL;DR: In this paper, a collector design for high-frequency SiGe:C HBTs without deep trenches and with low-resistance collectors formed by high-dose ion implantation after shallow trench formation was described.

TL;DR: In this article, the authors describe the architecture of the BiCMOS processes highlighting the modular scheme for the integration of the bipolar modules into a common CMOS platform and present design issues associated with the implanted collector wells and the key set of electrical HBT parameters.

TL;DR: In this paper, the authors demonstrate an extremely simple, flexible, and hence low-cost SiGe:C BiCMOS process with ample performance for the majority of high volume applications, which offers three HBT devices with f/sub T/BV/sub CEO/ values of 28 GHz/67 GHz/7.5 V, 52 GHz/98 GHz/3.8 V, and 75 GHz/ 90 GHz/2.4 V by adding only one mask to the underlying CMOS process.

TL;DR: In this article, a new collector construction for high-speed SiGe:C HBTs was proposed that substantially reduces the parasitic base collector capacitance by selectively underetering of the collector region.

TL;DR: SiGe:C pnp HBTs in a complementary bipolar CMOS flow with f/sub T//f/sub max/ values of 80 GHz/120 GHz at BV/sub CEO/ = 26 V and a ring oscillator delay of 89 ps were demonstrated in this paper.