This paper reviews recent progress and future directions of signal integrity design for high-speed digital circuits, focusing on four areas: signal propagation on transmission lines, discontinuity modeling and characterization, measurement techniques, and link-path design and analysis.

Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions

This paper presents a survey and classification of architectures for integrated circuit implementation of digital pulse-width modulators (DPWM) targeting digital control of high-frequency switching DC-DC power converters. Previously presented designs are identified as particular cases of the proposed classification. In order to optimize circuit resources in terms of occupied area and power consumption, a general architecture based on tapped delay lines is proposed, which includes segmentation of the input digital code to drive binary weighted delay cells and thermometer-decoded unary delay cells. Integrated circuit design of a particular example of the segmented DPWM is described. The segmented DPWM prototype chip operates at 1 MHz switching frequency and has low power consumption and very small silicon area (0.07 mm/sup 2/ in a standard 0.5 micron CMOS process). Experimental results validate the functionality of the proposed segmented DPWM.

Digital pulse width modulator architectures

A complete analysis on subharmonically injection-locked PLLs develops fundamental theory for subharmonic locking phenomenon. It explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue. All of the analyses are verified by real chip measurements. Two 20-GHz PLLs based on the proposed theory are designed and fabricated in 90-nm CMOS technology to demonstrate the superiority and robustness of this technique. The first chip aims at low-noise/low-power/high-divide-ratio design, achieving 149-fs rms jitter (integrated from 100 Hz to 1 GHz) while consuming 38 mW from a 1.3-V supply. The second prototype shoots for the lowest noise performance, presenting 85-fs rms jitter (the same integration interval) with a power dissipation of 105 mW. The jitter generation (from 50 kHz to 80 MHz) measures 48 fs, which is at least twice as small as that of any other known circuits.

Study of Subharmonically Injection-Locked PLLs

This paper presents a short review of time-to-digital and digital-to-time converters (TDCs and DTCs, respectively) adopting a time-mode signal-processing perspective. The primary definitions, operating principles, and basic building blocks are presented. The discussion applies to most, if not all, DTCs and TDCs. A series of voltage-controlled delay units are used as the primary building block of these converter circuits. When configured in a servo-loop manner, a very short time resolution is achievable with excellent manufacturing robustness. Such designs can be synthesized in field-programmable gate arrays (FPGAs) or constructed in custom silicon. TDCs and DTCs are not new, as they have extensively been used for making very accurate and repeatable time measurements in both the physics-related and semiconductor industry. Today, TDCs and DTCs are finding new applications in phase-locked loops and frequency synthesizers.

A Brief Introduction to Time-to-Digital and Digital-to-Time Converters

The article first discusses the major non-ideal issues of low-cost transmission media for over Gbps data transmissions - the frequency dispersion loss and channel noise. The former causes ISI in received signal, which presents difficulty for clock and data recovery at high frequencies and results higher BER. The latter further degrades the received signal quality and further limits the data transmission rate and transmission distance. Then, two equalization approaches - transmitter pre-emphasis and receiver equalization, are reviewed, in addition to various adaptation criteria and algorithms.

Equalization in high-speed communication systems

A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-/spl mu/m CMOS technology, occupies a total active area of 0.05 mm/sup 2/ and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of M=4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72/spl times/72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk).

/pdf/a-low-power-multiplying-dll-for-low-jitter-multigigahertz-55swzocsa2.pdf

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a first-order DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filtering and phase filtering are discussed. Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated.

/pdf/jitter-transfer-characteristics-of-delay-locked-loops-3aqti2wqug.pdf

Jitter transfer characteristics of delay-locked loops - theories and design techniques

A compact (1 mm /spl times/ 160 /spl mu/m) and low-power (80-mW) 0.18-/spl mu/m CMOS 3.125-Gb/s clock and data recovery circuit is described. The circuit utilizes injection locking to filter out high-frequency reference clock jitter and multiplying delay-locked loop duty-cycle distortions. The injection-locked slave oscillator output can have its output clocks interpolated by current steering the injecting clocks. A second-order clock and data recovery is introduced to perform the interpolation and is capable of tracking frequency offsets while exhibiting low phase wander.

/pdf/a-second-order-semi-digital-clock-recovery-circuit-based-on-5fkummvgtg.pdf

A second-order semi-digital clock recovery circuit based on injection locking

This paper presents a 622 Mbps to 8 Gbps transceiver in standard 0.13 /spl mu/m CMOS technology. Each receiver and transmitter macrocell has its dedicated clock multiplication unit (CMU) and clock/data recovery unit (CDR), providing simultaneous multi-rate operation for multiple lanes on a chip. The transmitter and receiver front-end use direct 4:1 multiplex and 1:4 demultiplexing, using multiple-phase quarter-rate clocks. An automatic phase offset cancellation scheme is used to eliminate the phase mismatch of the multiple clock phases. Each transceiver occupies an active area of less than 0.4 mm/sup 2/ and consumes 150 mW at maximum speed.

http://www.vlsisymposium.org/Past/03web/circuits/cir_pdf/C5p3.pdf

0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.

R. Senthinathan

Papers

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

Jitter transfer characteristics of delay-locked loops - theories and design techniques

A second-order semi-digital clock recovery circuit based on injection locking

0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os