Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.

/pdf/power-distribution-system-design-methodology-and-capacitor-lhl3j5lhjo.pdf

Power distribution system design methodology and capacitor selection for modern CMOS technology

Power and ground planes are required to have low impedance over a wide range of frequencies. Parallel ground and power planes in multilayer printed-circuit boards exhibit multiple resonances, which increase the impedance and also the radiation from the edge of the board. Resistive termination along the board edges reduces the resonance peaks. Simple and straightforward design expressions, simulated self and transfer impedances, as well as measured impedance plots are presented for power-ground planes.

Reducing simultaneous switching noise and EMI on ground/power planes by dissipative edge termination

Voltage noise characterization is an essential aspect of optimizing the shipped voltage of high-end processor based systems. Voltage noise, i.e. Variations in the supply voltage due to transient fluctuations on current, can negatively affect the robustness of the design if it is not properly characterized. Modeling and estimation of voltage noise in a pre-silicon setting is typically inadequate because it is difficult to model the chip/system packaging and power distribution network (PDN) parameters very precisely. Therefore, a systematic, direct measurement-based characterization of voltage noise in a post-silicon setting is mandatory in validating the robustness of the design. In this paper, we present a direct measurement-based voltage noise characterization of a state-of-the-art mainframe class multicoreprocessor. We develop a systematic methodology to generate noise stress marks. We study the sensitivity of noise in relation to the different parameters involved in noise generation: (a) stimulus sequence frequency, (b) supply current delta, (c) number of noise events and, (d) degree of alignment or synchronization of events in a multi-core context. By sensing per-core noise in amulti-core chip, we characterize the noise propagation across the cores. This insight opens up new opportunities for noise mitigation via workload mappings and dynamic voltage guard banding.

Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities

Power and ground planes should exhibit low impedance over a wide range of frequencies. Parallel ground and power planes in multilayer printed-circuit boards exhibit multiple resonances which increase the impedance and also the radiation from the board edge. Resistive termination along the board edges reduces the resonance peaks. Simple and straightforward design expressions, simulated self and transfer impedances, and measured impedance and radiation plots are presented for a pair of 10" by 10" planes with 31 mil FR4 dielectrics.

http://electrical-integrity.com/Paper_download_files/EPEP98_DET.pdf

While circuit and package designers have addressed microprocessor inductive noise issues in the past, multi-gigahertz clock frequencies and billion-transistor-level integration are exacerbating the problem, necessitating microarchitectural solutions. The large net on-die decoupling capacitance used to address this noise throughout the chip consumes substantial area and can cause a large leakage current. This paper proposes microarchitectural techniques to reduce high-frequency current variability, reducing the need for decoupling capacitors. We observe that we can control inductive noise by reducing current variability either in space (i.e., variability in usage of circuit blocks) or in time (i.e., variability within a circuit block across clock cycles). We propose pipeline muffling, a novel technique to reduce changes in the number of resources being utilized by controlling instruction issue, trading off some energy and performance to control di/dt in space. We also extend a previous technique, which incurs performance and energy degradation, and propose a priori current ramping to allow the current of a resource to ramp up ahead of usage, with virtually no performance loss, and ramp down immediately after usage, with little energy loss. Our techniques guarantee a worst-case bound on the di/dt, which is required to reduce the demand for decoupling capacitors, saving area and reducing leakage.

/pdf/pipeline-muffling-and-a-priori-current-ramping-architectural-42co31131u.pdf

Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise

Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBM's CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

CMOS microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity from clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50 to 200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBM's CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm MCM on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

R.W. Frech

Papers

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Mid-frequency simultaneous switching noise in computer systems