Diamond-like carbon: state of the art

The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Improving resolution in photolithography with a phase-shifting mask

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

Lithography is a field in which advances proceed at a swift pace. This book was written to address several needs, and the revisions for the second edition were made with those original objectives in mind. Many new topics have been included in this text commensurate with the progress that has taken place during the past few years, and several subjects are discussed in more detail. This book is intended to serve as an introduction to the science of microlithography for people who are unfamiliar with the subject. Topics directly related to the tools used to manufacture integrated circuits are addressed in depth, including such topics as overlay, the stages of exposure, tools, and light sources. This text also contains numerous references for students who want to investigate particular topics in more detail, and they provide the experienced lithographer with lists of references by topic as well. It is expected that the reader of this book will have a foundation in basic physics and chemistry. No topics will require knowledge of mathematics beyond elementary calculus.

Principles of Lithography

This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.

Nanoscale CMOS

A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

Process window based optical proximity correction of lithographic images

A general level-specific lithography optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175- and 150-nm ground rules. This three-step methodology-ruling out inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quantification using the total window metric. The optimal lithography strategy is pattern specific, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement techniques such as phase-shifting masks, annular illumination and optical proximity correction are essential in enlarging the inadequate process latitude of conventional lithography.

Level-specific lithography optimization for 1-Gb DRAM

Process windows are frequently generated from simulated aerial image profiles by use of a threshold model for the resist process, an assumption which is not accurate for many processes. In this paper, we present new computationally efficient methods for incorporating the effects of resist processing into simulated images. The First Order Model of development leads to the simple result that the resist linewidth W is smaller than the threshold linewidth Wthresh by an amount (Delta) W approximately equals 2 [ln(D(gamma) s)-1]/((gamma) s), where D is the resist thickness, (gamma) is the resist process non-linearity and s is the log-slope of the image. A Second Order Model based on a segmented development path is also presented. These models allow the prediction of resist linewidths based on calculated image profiles for any wet developed process: optical, X-ray or e-beam lithography, both positive and negative resists. The predictions of these models show good agreement with full PROLITH/2 resist profile simulations. We have also incorporated a Fickian diffusion of the intensity profile into our model, to account for acid diffusion, stepper vibration, lens aberrations, and other effects which reduce process resolution. Experimental process windows are well matched by such models, and are significantly different than threshold model predictions.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Approximate models for resist processing effects

A lithographic patterning method and mask set using a phase shift trim mask having mask dimensions increased in block size so as to remove previous exposure defects.

Lithographic patterning method and mask set therefor with light field trim mask

A method for determining if an undesirable feature on a photomask will adversely affect the performance of the semiconductor integrated circuit device that the mask is being used to create. The method includes inspecting the photomask for undesirable features and analyzing the designed features close to the defects. This analysis is performed on lithographic images that represent the image that is transferred onto the semiconductor wafer by the lithography process. This analysis takes into account the effect of variations that are present in the lithography process. Through knowledge of the effects of variations in mask critical dimension of a feature on the lithographic image of that feature, the analysis results in the assignment of an equivalent critical dimension error to the defect. This equivalent critical dimension error is then compared to the mask critical dimension error specification to determine whether or not the defect will adversely affect the device.

Richard A. Ferguson

Papers

Process window based optical proximity correction of lithographic images

Level-specific lithography optimization for 1-Gb DRAM

Approximate models for resist processing effects

Lithographic patterning method and mask set therefor with light field trim mask

Method of determining the printability of photomask defects