In this work, a simulation-based performance study of vertical super-thin body (VSTB) MOSFET vis-a-vis various other MOS devices was presented. Use of appropriate doping profile greatly improves on to off current ratio (ION/IOFF) and subthreshold swing (SS). Improvement in input characteristics (ID–VGS) by gate–source (G/S) and gate–drain (G/D) overlap technique was explained with the help of electron density, mobility, and velocity of the device in off and on-states. Device performance shows negligible deviations in presence of different effects like stress, strain, tunneling, and velocity saturation. VSTB FET supports the downscaling of device size by offering excellent electrostatic integrity and low supply voltage operation. Values of off-current (IOFF), peak on-current (ION), peak transconductance (gm), SS, and DIBL for channel length (L) of 20 nm are 0.00145 nA/µm, 327.85 µA/µm, 974 µS/µm, 65.1 mV/dec, and 39.6 mV/V, respectively. Noise impact on device performance for three different noise sources (diffusion, generation–recombination/G–R, and flicker noise) was studied at two different frequencies (f = 1 MHz and 10 GHz). Maximum values of unit-gain cut-off frequencies (fTmax) obtained for channel lengths (L) of 20, 25, and 30 nm are 86.26, 80.47, and 76.22 GHz, respectively.

Performance analysis of vertical super-thin body (VSTB) FET and its characteristics in presence of noise

Surface potential and drain current models for a physically based double halo metal–oxide–semiconductor-field-effect-transistor (MOSFET) are reported. The proposed models have been established in sub-threshold mode of MOSFET operation. The depletion layer depth used in the pseudo two dimensional Poisson’s equation comprises the effect of two symmetrical pocket implantations at both the ends of the channel region. In this effort, improvement in the investigation is brought in by taking lateral asymmetric channel owing to non-uniform doping. The conventional silicon-dioxide (SiO2) material is replaced with a promising high-k dielectric material hafnium oxide (HfO2) to analyze the surface potential and drain current models. Analytical results have been compared using Synopsys technology computer aided design (TCAD). Excellent conformities between the analytical models and simulations are observed.

Effects of Hafnium Oxide on Surface Potential and Drain Current Models for Subthreshold Short Channel Metal–Oxide–Semiconductor-Field-Effect-Transistor

We investigated vertical super-thin body (VSTB) FET performance in presence of different interface (HfO2/Si) trap distributions (uniform and Gaussian) and concentrations using TCAD tools. For trap concentration (TC) of 1013 eV−1 cm−2, the percentage change in on-to-off current ratio (Ion/Ioff) is 93.91% for uniform trap (UT) and 49.8% for Gaussian trap (GT) distribution. For the same TC, subthreshold swing (SS) shows percentage change of 5.1% for UT and 11.41% for GT distribution. Thus, the device performance shows good immunity for TC up to 1013 eV−1 cm−2. However, for TC = 1014 eV−1 cm−2 SS degrades significantly. The influence of traps on the cumulative effect of three noise sources (diffusion + generation–recombination/G–R + flicker) and on individual noise sources (G–R and diffusion) is explained qualitatively at low and high frequencies (f = 1 MHz and 10 GHz). The study shows that the overall noise cannot disturb the device performance at very high frequency. Various radio-frequency (RF) parameters like transconductance (gm), total input capacitance (Cgg), gate-drain capacitance (Cgd), unit-gain cutoff frequency (fT), and gain–bandwidth-product (GBP) are also studied for variation of trap types. For TC = 1014 eV−1 cm−2, the percentage change in fTmax (GBPmax) is − 21.43% (− 8%) for UT and − 22.86% (− 9.6%) for GT distribution.

An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics

This work presents a simulation study of the influence of temperature on the performance of dual material gate (DMG) vertical super-thin body (VSTB) FET. The introduction of DMG causes a drop in the off-state current (Ioff) by ~99.18% and DIBL by 20%. Drop in the Ioff enhances the on-to-off current ratio (Ion/Ioff) by ~98.85%. A rigorous investigation on temperature dependency of DC, analog/RF, and linearity metrics was carried out. The zero temperature coefficient (ZTC) bias point for the DMG device was observed to be nearly at a gate bias of VG = 0.41 V. Various DC figures of merit (FoM) such as subthreshold swing (SS), Ion/Ioff, and threshold voltage (VT) show improvement with temperature fall. Lowering in temperature also leads to enhanced analog/RF performance by offering superior gm, gd, Cgg, Cgd, maximum fT, maximum GBP, intrinsic delay, TGF, TFP, GFP, and GTFP. However, linearity metrics like gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point show better performance with an increase in temperature.

Study of Temperature Effect on Analog/RF and Linearity Performance of Dual Material Gate (DMG) Vertical Super-Thin Body (VSTB) FET

2D modeling based comprehensive analysis of short channel effects in DMG strained VSTB FET

In this paper, a 2-D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation. The analytical surface potential expression for gate-side surface and sidewall side surface has been modeled using parabolic surface potential approximation. The threshold voltage model for the VSTB FET has been derived by applying strong inversion criterion at the surface potential minimum value. The threshold voltage model for the VSTB FET has been analyzed by varying the body thickness, oxide thickness, and channel doping concentrations. The drain-induced barrier lowering and threshold voltage roll-off parameters are also extracted and analyzed for different body thicknesses. The models for surface potential and threshold voltage have been compared with the results obtained from the 2-D numerical device simulator and a very good agreement between the two has been observed.

Rimma Pirogova

Papers

2-D Analytical Modeling of Surface Potential and Threshold Voltage for Vertical Super-Thin Body FET