Multilayer neural networks trained with the back-propagation algorithm constitute the best example of a successful gradient based learning technique. Given an appropriate network architecture, gradient-based learning algorithms can be used to synthesize a complex decision surface that can classify high-dimensional patterns, such as handwritten characters, with minimal preprocessing. This paper reviews various methods applied to handwritten character recognition and compares them on a standard handwritten digit recognition task. Convolutional neural networks, which are specifically designed to deal with the variability of 2D shapes, are shown to outperform all other techniques. Real-life document recognition systems are composed of multiple modules including field extraction, segmentation recognition, and language modeling. A new learning paradigm, called graph transformer networks (GTN), allows such multimodule systems to be trained globally using gradient-based methods so as to minimize an overall performance measure. Two systems for online handwriting recognition are described. Experiments demonstrate the advantage of global training, and the flexibility of graph transformer networks. A graph transformer network for reading a bank cheque is also described. It uses convolutional neural network character recognizers combined with global training techniques to provide record accuracy on business and personal cheques. It is deployed commercially and reads several million cheques per day.

Gradient-based learning applied to document recognition

http://www.eecs.ucf.edu/~dcm/Teaching/COT4810-Spring2011/Literature/SensorNetworksSurvey.pdf

Wireless sensor networks: a survey

Networking together hundreds or thousands of cheap microsensor nodes allows users to accurately monitor a remote environment by intelligently combining the data from the individual nodes. These networks require robust wireless communication protocols that are energy efficient and provide low latency. We develop and analyze low-energy adaptive clustering hierarchy (LEACH), a protocol architecture for microsensor networks that combines the ideas of energy-efficient cluster-based routing and media access together with application-specific data aggregation to achieve good performance in terms of system lifetime, latency, and application-perceived quality. LEACH includes a new, distributed cluster formation technique that enables self-organization of large numbers of nodes, algorithms for adapting clusters and rotating cluster head positions to evenly distribute the energy load among all the nodes, and techniques to enable distributed signal processing to save communication resources. Our results show that LEACH can improve system lifetime by an order of magnitude compared with general-purpose multihop approaches.

/pdf/an-application-specific-protocol-architecture-for-wireless-1s7y9fiv40.pdf

An application-specific protocol architecture for wireless microsensor networks

Alhussein Abouzeid Rensselaer Polytechnic Institute Raviraj Adve University of Toronto Dharma Agrawal University of Cincinnati Walid Ahmed Tyco M/A-COM Sonia Aissa University of Quebec, INRSEMT Huseyin Arslan University of South Florida Nallanathan Arumugam National University of Singapore Saewoong Bahk Seoul National University Claus Bauer Dolby Laboratories Brahim Bensaou Hong Kong University of Science and Technology Rick Blum Lehigh University Michael Buehrer Virginia Tech Antonio Capone Politecnico di Milano Javier Gómez Castellanos National University of Mexico Claude Castelluccia INRIA Henry Chan The Hong Kong Polytechnic University Ajit Chaturvedi Indian Institute of Technology Kanpur Jyh-Cheng Chen National Tsing Hua University Yong Huat Chew Institute for Infocomm Research Tricia Chigan Michigan Tech Dong-Ho Cho Korea Advanced Institute of Science and Tech. Jinho Choi University of New South Wales Carlos Cordeiro Philips Research USA Laurie Cuthbert Queen Mary University of London Arek Dadej University of South Australia Sajal Das University of Texas at Arlington Franco Davoli DIST University of Genoa Xiaodai Dong, University of Alberta Hassan El-sallabi Helsinki University of Technology Ozgur Ercetin Sabanci University Elza Erkip Polytechnic University Romano Fantacci University of Florence Frank Fitzek Aalborg University Mario Freire University of Beira Interior Vincent Gaudet University of Alberta Jairo Gutierrez University of Auckland Michael Hadjitheodosiou University of Maryland Zhu Han University of Maryland College Park Christian Hartmann Technische Universitat Munchen Hossam Hassanein Queen's University Soong Boon Hee Nanyang Technological University Paul Ho Simon Fraser University Antonio Iera University "Mediterranea" of Reggio Calabria Markku Juntti University of Oulu Stefan Kaiser DoCoMo Euro-Labs Nei Kato Tohoku University Dongkyun Kim Kyungpook National University Ryuji Kohno Yokohama National University Bhaskar Krishnamachari University of Southern California Giridhar Krishnamurthy Indian Institute of Technology Madras Lutz Lampe University of British Columbia Bjorn Landfeldt The University of Sydney Peter Langendoerfer IHP Microelectronics Technologies Eddie Law Ryerson University in Toronto

Wireless communications

https://www.cs.montana.edu/courses/csci566/Ref/CR-Survey.pdf

NeXt generation/dynamic spectrum access/cognitive radio wireless networks: a survey

Modern electronic systems contain a mix of software running on general-purpose programmable processors, algorithms hardwired into dedicated hardware such as custom boards and chips, electromechanical components, and mechanical interconnect and packaging. Far more time Is spent in designing the boards, writing the software to drive, and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Therefore a systems perspective of the design process is essential, as opposed to the conventional "chip-focused" approach. A design framework, called SIERA, for application-specific systems is described in which higher level aspects of system design, including software, multichip design issues present at the board level, and hardware-software integration are addressed, in addition to the design of individual custom chips. A high-level description of the system as a network of processes is mapped to a system architecture template consisting of multiple boards using dedicated hardware modules and ASIC's as well as software processes running on programmable hardware modules. Application of SIERA's design methodology to a multisensory robot control system is also presented. >

SIERA: a unified framework for rapid-prototyping of system-level hardware and software

Deep depletion in both p-type and n-type substrates can be induced by minority carriers tunneling away from the substrate. When this occurs, tunneling current becomes saturated at the rate of carrier generation in the substrate, with the excess applied voltage dropped across the deep-depletion region. We present a quantitative model for this phenomenon based on balancing the tunneling current and the space-charge generation current. Conversely, the usual transient deep depletion in n-type substrate MOS capacitors can be terminated by tunneling-induced electron-hole pair generation, except for those with ultrathin oxides (<40 A).

Creation and termination of substrate deep depletion in thin oxide MOS Capacitors by charge tunneling

Transmitting multimedia data over a code-division multiple access (CDMA) channel presents a new set of challenges: data demands will sometimes exceed the system capacity, in which case the system must make the most efficient use of its limited resources. In this paper, we present our approach for unifying power control, variable forward error correction (VFEC), and scheduling for a downlink system by allocating the system resources. The resources we consider are: fixed bandwidth available for each user and the transmit power budget for each cell. Our objective is to maximize the overall system satisfaction, which we call "system utility." This objective is achieved by applying a distributed algorithm which divides the overall optimization problem into a hierarchy of three levels (system, cell, and user), with each performing independent and parallel optimizations. We perform simulation-based evaluation of the system performance with a simple cell structure and uniformly distributed users. The system is simulated using a specific utility function: the step function. Finally, several practical issues regarding the implementation are investigated.

Integrating power control, error correction coding, and scheduling for a CDMA downlink system

An approach is presented for minimizing power consumption in algorithm AN APPROACH FOR POWER MINIMIZATION USING TRANSFORMATIONS iantha Chandrakasan?, Miodrag Potkonjak??, Jan Rabaey?, Robert Broderseri? ?EECS Department, University of California at Berkeley. ?+C & C Research Laboratories, NEC USA, Princeton.

An Approach For Power Minimization Using Transformations

Complex digital systems are designed with hardware modules which interact by transferring information and synchronizing their inputs and outputs. The modules can be constructed from a variety of single IC components to subsystems, and typically they have incompatible I10 and communication protocols. A large portion of the integration time is thus devoted to designing the interfaces (also a module) between interacting modules. This paper presents a design methodology and high-level synthesis techniques for integrating hardware modules into a system. The interface between modules, which can obey arbitrary protocols, is generated from a high-level specification developed especially for describing inter-module communication. Central to the design methodology are libraries which contain system-level module generators and a strategy to capture the protocol and timing information necessary for interface synthesis. The main impact of this work is raising the interface design abstraction and reducing the effort required from a designer to produce a system using various IC technologies.

Robert W. Brodersen

Papers

SIERA: a unified framework for rapid-prototyping of system-level hardware and software

Creation and termination of substrate deep depletion in thin oxide MOS Capacitors by charge tunneling

Integrating power control, error correction coding, and scheduling for a CDMA downlink system

An Approach For Power Minimization Using Transformations

Design of system interface modules