Multilayer neural networks trained with the back-propagation algorithm constitute the best example of a successful gradient based learning technique. Given an appropriate network architecture, gradient-based learning algorithms can be used to synthesize a complex decision surface that can classify high-dimensional patterns, such as handwritten characters, with minimal preprocessing. This paper reviews various methods applied to handwritten character recognition and compares them on a standard handwritten digit recognition task. Convolutional neural networks, which are specifically designed to deal with the variability of 2D shapes, are shown to outperform all other techniques. Real-life document recognition systems are composed of multiple modules including field extraction, segmentation recognition, and language modeling. A new learning paradigm, called graph transformer networks (GTN), allows such multimodule systems to be trained globally using gradient-based methods so as to minimize an overall performance measure. Two systems for online handwriting recognition are described. Experiments demonstrate the advantage of global training, and the flexibility of graph transformer networks. A graph transformer network for reading a bank cheque is also described. It uses convolutional neural network character recognizers combined with global training techniques to provide record accuracy on business and personal cheques. It is deployed commercially and reads several million cheques per day.

Gradient-based learning applied to document recognition

http://www.eecs.ucf.edu/~dcm/Teaching/COT4810-Spring2011/Literature/SensorNetworksSurvey.pdf

Wireless sensor networks: a survey

Networking together hundreds or thousands of cheap microsensor nodes allows users to accurately monitor a remote environment by intelligently combining the data from the individual nodes. These networks require robust wireless communication protocols that are energy efficient and provide low latency. We develop and analyze low-energy adaptive clustering hierarchy (LEACH), a protocol architecture for microsensor networks that combines the ideas of energy-efficient cluster-based routing and media access together with application-specific data aggregation to achieve good performance in terms of system lifetime, latency, and application-perceived quality. LEACH includes a new, distributed cluster formation technique that enables self-organization of large numbers of nodes, algorithms for adapting clusters and rotating cluster head positions to evenly distribute the energy load among all the nodes, and techniques to enable distributed signal processing to save communication resources. Our results show that LEACH can improve system lifetime by an order of magnitude compared with general-purpose multihop approaches.

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An application-specific protocol architecture for wireless microsensor networks

Alhussein Abouzeid Rensselaer Polytechnic Institute Raviraj Adve University of Toronto Dharma Agrawal University of Cincinnati Walid Ahmed Tyco M/A-COM Sonia Aissa University of Quebec, INRSEMT Huseyin Arslan University of South Florida Nallanathan Arumugam National University of Singapore Saewoong Bahk Seoul National University Claus Bauer Dolby Laboratories Brahim Bensaou Hong Kong University of Science and Technology Rick Blum Lehigh University Michael Buehrer Virginia Tech Antonio Capone Politecnico di Milano Javier Gómez Castellanos National University of Mexico Claude Castelluccia INRIA Henry Chan The Hong Kong Polytechnic University Ajit Chaturvedi Indian Institute of Technology Kanpur Jyh-Cheng Chen National Tsing Hua University Yong Huat Chew Institute for Infocomm Research Tricia Chigan Michigan Tech Dong-Ho Cho Korea Advanced Institute of Science and Tech. Jinho Choi University of New South Wales Carlos Cordeiro Philips Research USA Laurie Cuthbert Queen Mary University of London Arek Dadej University of South Australia Sajal Das University of Texas at Arlington Franco Davoli DIST University of Genoa Xiaodai Dong, University of Alberta Hassan El-sallabi Helsinki University of Technology Ozgur Ercetin Sabanci University Elza Erkip Polytechnic University Romano Fantacci University of Florence Frank Fitzek Aalborg University Mario Freire University of Beira Interior Vincent Gaudet University of Alberta Jairo Gutierrez University of Auckland Michael Hadjitheodosiou University of Maryland Zhu Han University of Maryland College Park Christian Hartmann Technische Universitat Munchen Hossam Hassanein Queen's University Soong Boon Hee Nanyang Technological University Paul Ho Simon Fraser University Antonio Iera University "Mediterranea" of Reggio Calabria Markku Juntti University of Oulu Stefan Kaiser DoCoMo Euro-Labs Nei Kato Tohoku University Dongkyun Kim Kyungpook National University Ryuji Kohno Yokohama National University Bhaskar Krishnamachari University of Southern California Giridhar Krishnamurthy Indian Institute of Technology Madras Lutz Lampe University of British Columbia Bjorn Landfeldt The University of Sydney Peter Langendoerfer IHP Microelectronics Technologies Eddie Law Ryerson University in Toronto

Wireless communications

https://www.cs.montana.edu/courses/csci566/Ref/CR-Survey.pdf

NeXt generation/dynamic spectrum access/cognitive radio wireless networks: a survey

SUMMARY This paper describes a system architecture along with signal processing technique which allows a reduction in the complexity of a 3.1–10.6 GHz Ultra-Wideband radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end down-converts the signal frequency by subsampling, thus, requiring substantially less hardware than a traditional narrowband approach. However, the simplified receiver front end shows a high sensitivity to timing offset. By proposing an analytic signal processing technique, the vulnerability of timing offset is mitigated; furthermore, a time resolution finer than the sampling period is achieved, which is useful for locationing or ranging applications. Analysis and simulations of system specifications are also provided in this paper.

/pdf/a-subsampling-uwb-impulse-radio-architecture-utilizing-76qdozvib8.pdf

A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling

A flexible, low power, "mostly-digital", DC-1 GHz impulse-UWB transceiver front-end is presented By duty-cycling nearly all of the circuitry with the pulse rate, power consumption of 570 muW (RX) and 350 muW (TX) is presented at 1 Mpulse/s with 1-bit, 192 GSample/s sampling, 50 Omega input matching, and 42 dB of gain at 11 V Additionally, the transceiver allows for variable modulation (PAM, PPM or both), variable gain (0 to 42dB), independent timing control for each block, variable input impedance and pulse shape generation, limited pulling of the oscillator frequency, and gain stage offset trimming to 1 mV

A Flexible, Low Power, DC-1GHz Impulse-UWB Transceiver Front-end

This paper presents the design and implementation of BORPHpsilas kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics resembling that of conventional UNIX file I/Os, an FPGA accesses the file system through a special hardware system call interface. By extending the semantics of a UNIX pipe, a single file system access mechanism is used for both regular file I/O, as well as for hardware/software and hardware/hardware data streaming. An FPGA design may switch between different communication modes dynamically during run time by means of file redirection. Design trade-offs among system manageability, user usability and application performance are explored. An example of constructing a video processing system during run time using commodity software and FPGA applications connected by pipes is used to demonstrate the feasibility and potential of such FPGA-centric file system access capability.

/pdf/file-system-access-from-reconfigurable-fpga-hardware-6xii9l5e0c.pdf

File system access from reconfigurable FPGA hardware processes in BORPH

The authors have identified the resolution/decimation tradeoff in practical delta-sigma A/D converters and the add-rate and memory requirements for first-stage decimators, FIR filters can be expressed in a general z-domain structure that scales directly with decimation. A time-domain procedure facilitates computing the effect of practical decimation filters on DSM (delta-sigma modulator) noise, permitting a systematic comparison of electrical performance. Automatically minimized logic networks are an efficient means of realizing compact impulse-response storage to implement these decimators in automatically generated custom IC form. >

Monolithic decimation filtering for custom delta-sigma A/D converters

The authors describe a clock-free design approach that facilitates modular design without compromising global performance. The goal is to support rapid prototyping of real-time digital signal processing systems with a minimum amount of design effort. The approach allows the scaling up of small prototype systems to very large multiboard systems without concern for global timing problems. The authors address the interconnect schemes applicable to real-time systems and the circuit design techniques for a clock-free implementation. >

Robert W. Brodersen

Papers

A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling

A Flexible, Low Power, DC-1GHz Impulse-UWB Transceiver Front-end

File system access from reconfigurable FPGA hardware processes in BORPH

Monolithic decimation filtering for custom delta-sigma A/D converters

Design of clock-free asynchronous systems for real-time signal processing