Multilayer neural networks trained with the back-propagation algorithm constitute the best example of a successful gradient based learning technique. Given an appropriate network architecture, gradient-based learning algorithms can be used to synthesize a complex decision surface that can classify high-dimensional patterns, such as handwritten characters, with minimal preprocessing. This paper reviews various methods applied to handwritten character recognition and compares them on a standard handwritten digit recognition task. Convolutional neural networks, which are specifically designed to deal with the variability of 2D shapes, are shown to outperform all other techniques. Real-life document recognition systems are composed of multiple modules including field extraction, segmentation recognition, and language modeling. A new learning paradigm, called graph transformer networks (GTN), allows such multimodule systems to be trained globally using gradient-based methods so as to minimize an overall performance measure. Two systems for online handwriting recognition are described. Experiments demonstrate the advantage of global training, and the flexibility of graph transformer networks. A graph transformer network for reading a bank cheque is also described. It uses convolutional neural network character recognizers combined with global training techniques to provide record accuracy on business and personal cheques. It is deployed commercially and reads several million cheques per day.

Gradient-based learning applied to document recognition

http://www.eecs.ucf.edu/~dcm/Teaching/COT4810-Spring2011/Literature/SensorNetworksSurvey.pdf

Wireless sensor networks: a survey

Networking together hundreds or thousands of cheap microsensor nodes allows users to accurately monitor a remote environment by intelligently combining the data from the individual nodes. These networks require robust wireless communication protocols that are energy efficient and provide low latency. We develop and analyze low-energy adaptive clustering hierarchy (LEACH), a protocol architecture for microsensor networks that combines the ideas of energy-efficient cluster-based routing and media access together with application-specific data aggregation to achieve good performance in terms of system lifetime, latency, and application-perceived quality. LEACH includes a new, distributed cluster formation technique that enables self-organization of large numbers of nodes, algorithms for adapting clusters and rotating cluster head positions to evenly distribute the energy load among all the nodes, and techniques to enable distributed signal processing to save communication resources. Our results show that LEACH can improve system lifetime by an order of magnitude compared with general-purpose multihop approaches.

/pdf/an-application-specific-protocol-architecture-for-wireless-1s7y9fiv40.pdf

An application-specific protocol architecture for wireless microsensor networks

Alhussein Abouzeid Rensselaer Polytechnic Institute Raviraj Adve University of Toronto Dharma Agrawal University of Cincinnati Walid Ahmed Tyco M/A-COM Sonia Aissa University of Quebec, INRSEMT Huseyin Arslan University of South Florida Nallanathan Arumugam National University of Singapore Saewoong Bahk Seoul National University Claus Bauer Dolby Laboratories Brahim Bensaou Hong Kong University of Science and Technology Rick Blum Lehigh University Michael Buehrer Virginia Tech Antonio Capone Politecnico di Milano Javier Gómez Castellanos National University of Mexico Claude Castelluccia INRIA Henry Chan The Hong Kong Polytechnic University Ajit Chaturvedi Indian Institute of Technology Kanpur Jyh-Cheng Chen National Tsing Hua University Yong Huat Chew Institute for Infocomm Research Tricia Chigan Michigan Tech Dong-Ho Cho Korea Advanced Institute of Science and Tech. Jinho Choi University of New South Wales Carlos Cordeiro Philips Research USA Laurie Cuthbert Queen Mary University of London Arek Dadej University of South Australia Sajal Das University of Texas at Arlington Franco Davoli DIST University of Genoa Xiaodai Dong, University of Alberta Hassan El-sallabi Helsinki University of Technology Ozgur Ercetin Sabanci University Elza Erkip Polytechnic University Romano Fantacci University of Florence Frank Fitzek Aalborg University Mario Freire University of Beira Interior Vincent Gaudet University of Alberta Jairo Gutierrez University of Auckland Michael Hadjitheodosiou University of Maryland Zhu Han University of Maryland College Park Christian Hartmann Technische Universitat Munchen Hossam Hassanein Queen's University Soong Boon Hee Nanyang Technological University Paul Ho Simon Fraser University Antonio Iera University "Mediterranea" of Reggio Calabria Markku Juntti University of Oulu Stefan Kaiser DoCoMo Euro-Labs Nei Kato Tohoku University Dongkyun Kim Kyungpook National University Ryuji Kohno Yokohama National University Bhaskar Krishnamachari University of Southern California Giridhar Krishnamurthy Indian Institute of Technology Madras Lutz Lampe University of British Columbia Bjorn Landfeldt The University of Sydney Peter Langendoerfer IHP Microelectronics Technologies Eddie Law Ryerson University in Toronto

Wireless communications

https://www.cs.montana.edu/courses/csci566/Ref/CR-Survey.pdf

NeXt generation/dynamic spectrum access/cognitive radio wireless networks: a survey

We propose a floating-point to fixed-point conversion (FFC) methodology for digital VLSI signal processing systems. The past techniques used to facilitate FFC are first reviewed, followed by a description based on a statistical approach and global optimization which allows a high degree of automation.

/pdf/an-automated-floating-point-to-fixed-point-conversion-4k2c79wp51.pdf

An automated floating-point to fixed-point conversion methodology

The impact of scattering condition and array configuration on performances are inseparable in early analyses of multiple-antenna systems. An array-independent scattering model is introduced where three basic scattering mechanisms are modeled. Performance results become more intrinsic property of the scattering channel itself. For linear arrays of length L in an environment of total angle spread |Omega|, the ergodic capacity is shown to increase linearly with L|Omega| for large arrays. When antenna arrays reduce to practical sizes, the capacity scaling depends on the signal-to-noise ratio (SNR) as well. This implies that the number of antennas used should also depend on the SNR. In terms of outage capacity, the tradeoff between spatial multiplexing gain and diversity gain is shown to be very sensitive to the underlying scattering mechanisms. Finally, as |Omega| varies with the propagation range, the tradeoff among multiplexing gain, diversity gain, and propagation range is studied

/pdf/impact-of-scattering-on-the-capacity-diversity-and-4c6aiabseu.pdf

Impact of scattering on the capacity, diversity, and propagation range of multiple-antenna channels

An integrated CAD system for the automated design of digital signal-processing (DSP) circuits for audio and telecommunication applications is described. The system uses as unique input a symbolic description of algorithm. This representation is translated into an actual layout using a two-step process. First, the symbolic input is mapped into the target architecture, which consists basically of a set of concurrent processors and dedicated I/O circuitry. The resulting hardware configuration is compiled into a layout description through a full exploitation of the hierarchy and the modularity of the architecture, calling consecutively a tiler, a floorplanner, and a global placement and routing tool. All these layout generation tools are able to support a wide range of technologies. The provision of a dedicated register transfer level simulator allows for the efficient debugging and algorithmic checking of the real-time operating signal-processing algorithms. The efficiency and the usefulness of this design methodology has been demonstrated by multiple examples. Experiments have shown that the use of these techniques can reduce the complete design process to a few months.

An Integrated Automated Layout Generation System for DSP Circuits

1. Introduction and History R.W. Brodersen. Part I: Framework and Design Entry. 2. The OCT Data Manager R. Spickelmier, B.C. Richards. 3. Lager OCT Policy and the SDL Language B.C. Richards. 4. Schematic Entry B. Reese. 5. Design Management B.C. Richards. 6. Design Post-Processing M. Thaler, B.C. Richards. Part II: Silicon Assembly. 7. Hierarchical Tiling J. Sun, B.C. Richards. 8. Standard Cell Design B. Reese, B. Boes. 9. Interactive Floorplanning Seungjun Lee, J. Rabaey. 10. Datapath Generation M. Srivastava. 11. Pad Routing E. Lettang. Part III: Verification and Testing. 12. Design Verification Wun-Tsin Jao, R. Jain. 13. Behavior and Switch Level Simulation L. Svensson, L.E. Thon, Seungjun Lee. 14. Chip and Board Testing K.T. Kornegay. Part IV: Behavioral Synthesis. 15. DSP Specification Using the Silage Language P. Hilfinger, J. Rabaey. 16. Synthesis of Datapath Architectures J. Rabaey, Chin-min Chu, Phu Hoang, M. Potkonjak. 17. From C to Silicon L.E. Thon, K. Rimey, L. Svensson. 18. An FIR Filter Generator P. Yang, R. Jain. Part V: Applications. 19. The PUMA Processor L.E. Thon. 20. Radon Transform Using the PPPE W.B. Baringer. 21. Speech Recognition A. Stoelzle. 22. Conclusions and Future Work R.W. Brodersen. Appendix A: Design Example B.C. Richards. Appendix B: Training and Distribution B. Reese. Index.

Anatomy of a Silicon Compiler

Advances in FPGA-based reconfigurable computers have made them a viable computing platform for a vast variety of computation demanding areas such as bioinformatics, speech recognition, and high-end digital signal processing. The lack of common, intuitive operating system support, however, hinders their wide deployment. This paper presents BORPH, an operating system frame-work for FPGA-based reconfigurable computers with a goal to ease and accelerate development of high-level applications to run on these computers. It provides kernel support for FPGA resources by extending a standard Linux operating system. Users therefore compile and execute hardware processes on FPGA resources the same way they run software processes on conventional processor-based systems. The operating system offers run-time general file system support to hardware processes as if they were software. Furthermore, a virtual file system is built to allow access to memories and registers defined in the FPGA, which provides communication links with running hardware processes. Increased productivities have been observed for high-level application developers, who have few previous experiences in hardware design, to implement complex mixed software/hardware designs on a FPGA-based reconfigurable computer running BORPH.

/pdf/improving-usability-of-fpga-based-reconfigurable-computers-34y5a2bx9o.pdf

Robert W. Brodersen

Papers

An automated floating-point to fixed-point conversion methodology

Impact of scattering on the capacity, diversity, and propagation range of multiple-antenna channels

An Integrated Automated Layout Generation System for DSP Circuits

Anatomy of a Silicon Compiler

Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support