Multilayer neural networks trained with the back-propagation algorithm constitute the best example of a successful gradient based learning technique. Given an appropriate network architecture, gradient-based learning algorithms can be used to synthesize a complex decision surface that can classify high-dimensional patterns, such as handwritten characters, with minimal preprocessing. This paper reviews various methods applied to handwritten character recognition and compares them on a standard handwritten digit recognition task. Convolutional neural networks, which are specifically designed to deal with the variability of 2D shapes, are shown to outperform all other techniques. Real-life document recognition systems are composed of multiple modules including field extraction, segmentation recognition, and language modeling. A new learning paradigm, called graph transformer networks (GTN), allows such multimodule systems to be trained globally using gradient-based methods so as to minimize an overall performance measure. Two systems for online handwriting recognition are described. Experiments demonstrate the advantage of global training, and the flexibility of graph transformer networks. A graph transformer network for reading a bank cheque is also described. It uses convolutional neural network character recognizers combined with global training techniques to provide record accuracy on business and personal cheques. It is deployed commercially and reads several million cheques per day.

Gradient-based learning applied to document recognition

http://www.eecs.ucf.edu/~dcm/Teaching/COT4810-Spring2011/Literature/SensorNetworksSurvey.pdf

Wireless sensor networks: a survey

Networking together hundreds or thousands of cheap microsensor nodes allows users to accurately monitor a remote environment by intelligently combining the data from the individual nodes. These networks require robust wireless communication protocols that are energy efficient and provide low latency. We develop and analyze low-energy adaptive clustering hierarchy (LEACH), a protocol architecture for microsensor networks that combines the ideas of energy-efficient cluster-based routing and media access together with application-specific data aggregation to achieve good performance in terms of system lifetime, latency, and application-perceived quality. LEACH includes a new, distributed cluster formation technique that enables self-organization of large numbers of nodes, algorithms for adapting clusters and rotating cluster head positions to evenly distribute the energy load among all the nodes, and techniques to enable distributed signal processing to save communication resources. Our results show that LEACH can improve system lifetime by an order of magnitude compared with general-purpose multihop approaches.

/pdf/an-application-specific-protocol-architecture-for-wireless-1s7y9fiv40.pdf

An application-specific protocol architecture for wireless microsensor networks

Alhussein Abouzeid Rensselaer Polytechnic Institute Raviraj Adve University of Toronto Dharma Agrawal University of Cincinnati Walid Ahmed Tyco M/A-COM Sonia Aissa University of Quebec, INRSEMT Huseyin Arslan University of South Florida Nallanathan Arumugam National University of Singapore Saewoong Bahk Seoul National University Claus Bauer Dolby Laboratories Brahim Bensaou Hong Kong University of Science and Technology Rick Blum Lehigh University Michael Buehrer Virginia Tech Antonio Capone Politecnico di Milano Javier Gómez Castellanos National University of Mexico Claude Castelluccia INRIA Henry Chan The Hong Kong Polytechnic University Ajit Chaturvedi Indian Institute of Technology Kanpur Jyh-Cheng Chen National Tsing Hua University Yong Huat Chew Institute for Infocomm Research Tricia Chigan Michigan Tech Dong-Ho Cho Korea Advanced Institute of Science and Tech. Jinho Choi University of New South Wales Carlos Cordeiro Philips Research USA Laurie Cuthbert Queen Mary University of London Arek Dadej University of South Australia Sajal Das University of Texas at Arlington Franco Davoli DIST University of Genoa Xiaodai Dong, University of Alberta Hassan El-sallabi Helsinki University of Technology Ozgur Ercetin Sabanci University Elza Erkip Polytechnic University Romano Fantacci University of Florence Frank Fitzek Aalborg University Mario Freire University of Beira Interior Vincent Gaudet University of Alberta Jairo Gutierrez University of Auckland Michael Hadjitheodosiou University of Maryland Zhu Han University of Maryland College Park Christian Hartmann Technische Universitat Munchen Hossam Hassanein Queen's University Soong Boon Hee Nanyang Technological University Paul Ho Simon Fraser University Antonio Iera University "Mediterranea" of Reggio Calabria Markku Juntti University of Oulu Stefan Kaiser DoCoMo Euro-Labs Nei Kato Tohoku University Dongkyun Kim Kyungpook National University Ryuji Kohno Yokohama National University Bhaskar Krishnamachari University of Southern California Giridhar Krishnamurthy Indian Institute of Technology Madras Lutz Lampe University of British Columbia Bjorn Landfeldt The University of Sydney Peter Langendoerfer IHP Microelectronics Technologies Eddie Law Ryerson University in Toronto

Wireless communications

https://www.cs.montana.edu/courses/csci566/Ref/CR-Survey.pdf

NeXt generation/dynamic spectrum access/cognitive radio wireless networks: a survey

A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4times4 MIMO signal processing.

/pdf/asic-design-and-verification-in-an-fpga-environment-15t2je6bvu.pdf

ASIC Design and Verification in an FPGA Environment

We have shown a prototype user interface for the InfoPad, a portable terminal with multi-modal input and multimedia output. We believe that many of the people who could benefit from inexpensive, portable, networked terminals are not computer experts, and we are therefore designing the InfoPad and its user interface to be more like a notebook than a workstation. The InfoPad’s main features are: ● Portabilityy ●Continuous network connectivity using a highbandwidth radio link ● Pen input with handwriting recognition ● Audio input with speech recognition ● Full-motion video playback with synchronized audio The InfoPad’s unique input and output characteristics offer challenges and opportunities for user interface design. We are prototyping applications and user interfaces to explore how handwriting and voice recognition may best be used together. We believe that the lessons we will learn can be applied to other multi-modal platforms.

A prototype user interface for a mobile multimedia terminal

This paper describes techniques and issues involved in the design of lowpower VLSI circuits and systems. This work has been motivated by emerging battery operated applications that require extreme computation in portable environments. The four degrees of freedom available for the design of low-power VLSI Technology, Circuit Approaches, Architectures, and Algorithms are reviewed and the relative gains to be expected from each are presented.

Low-power Signal Processing Systems

Most existing analyses of quantization effects are given under the condition that all decision-making blocks, if they exist in a system, produce identical decisions in both fixed-point and infinite-precision (IP) implementations. However, in doing floating-point to fixed-point conversion (FFC), a fixed-point design with occasional decision errors may still be an acceptable approximation of the IP system. We study the effect of this decision error, and relate its probability to the fixed-point data types. Our previous FFC methodology is then extended to include systems with possible decision errors due to quantization. The extended approach is applied to both CORDIC and a BPSK transceiver.

Floating-point to fixed-point conversion with decision errors due to quantization

Preface. 1. Introduction. 2. Modulation, Multiple Access, and How Radio Waves Behave Indoors. 3. System Overview: The Broadband CDMA Downlink. 4. Transmit Architecture and The Baseband Modulator Chip. 5. Broadband RF Transmission and Modulation. 6. The Receiver: Analog RF Front-End. 7. The Receiver: Baseband Analog Processing. 8. The Receiver: Baseband Spread-Spectrum Digital Signal Processor. 9. The Matched-Filter Correlator. 10. Conclusions and Future Directions. Index.

Robert W. Brodersen

Papers

ASIC Design and Verification in an FPGA Environment

A prototype user interface for a mobile multimedia terminal

Low-power Signal Processing Systems

Floating-point to fixed-point conversion with decision errors due to quantization

Low-Power CMOS Wireless Communications: A Wideband CDMA System Design