R
Rourab Paul
Researcher at Siksha O Anusandhan University
Publications - 51
Citations - 243
Rourab Paul is an academic researcher from Siksha O Anusandhan University. The author has contributed to research in topics: Field-programmable gate array & Encryption. The author has an hindex of 6, co-authored 43 publications receiving 155 citations. Previous affiliations of Rourab Paul include Indian Institute of Technology Kanpur & Information Technology University.
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A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication
TL;DR: A simpler RC4 hardware design providing higher throughput is proposed in which 1-byte is processed in 1-clock, and the swapping is directly executed using a MUX-DEMUX combination.
Journal ArticleDOI
Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm
TL;DR: A pipelined architecture of a high speed network security processor (NSP) for SSL/TLS protocol is implemented on a system on chip (SoC) where hardware information of all encryption, hashing and key exchange algorithms are stored in Secure Digital (SD) card in terms of bit files.
Proceedings ArticleDOI
Real time communication between multiple FPGA systems in multitasking environment using RTOS
TL;DR: This research work proposes the design and implementation of a real-time FPGA based application, which demonstrates the creation ofreal-time process tasks in FGPA systems for successful real- time communication between multiple FPGAs.
Proceedings ArticleDOI
A novel AES-256 implementation on FPGA using co-processor based architecture
TL;DR: Hardware design for implementing cryptographic algorithm on various hardware platforms like application specific integrated circuit (ASIC), field programmable gate array (FPGA) and micro-controllers is needed in terms of larger key values, higher throughput and less resource utilization.
Proceedings ArticleDOI
Novel architecture of modular exponent on reconfigurable system
TL;DR: This paper has proposed the design and implementation of modulus exponent operation in three different ways namely single clock architecture, sequential architecture and a processor core based architecture and shows that the design is better in terms of execution speed and hardware utilization in comparison with the existing research work.