We have studied the hybrid bonding process with a copper (Cu)/polyimide (PI) system by optimizing aqueous acid treatment, height control of Cu protrusion, and temporary/permanent bonding conditions for practical use. The study found that the treatment with an aqueous solution of citric or ascorbic acid and 80 nm-protrusion contributed to the improvement in the bonding yield of Cu electrodes. The suitable temperature and pressure of the permanent bonding were determined at 250 °C and 5 MPa, and the mechanically tough junctions for both Cu-Cu and PI-PI interface were successfully achieved with relatively low resistance.

Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide Systems

We have investigated the effect of an extremely large and relatively ordered Cu grains on the yield of Cu-Cu direct bonding/Cu-SiO2 hybrid bonding. Both modified electroplating method and the post processing have resulted into the formation of 10 – 15 μm large Cu grains before Cu-Cu direct bonding/CuSiO2 hybrid bonding. Employing such large and oriented grains, we have successfully carried out Cu-SiO2 hybrid bonding using 5 μm-size Cu electrodes at 10 μm-pitch values. The microstructural evaluation confirmed the formation relatively oriented Cu-grains. The more tensile nature of oriented Cu grains formed by modified electroplating and post processing might facilitate the Cu diffusion during the Cu-Cu direct/Cu-SiO2hybrid bonding.

Cu-SiO2 Hybrid Bonding Yield Enhancement Through Cu Grain Enlargement

This paper deals with multichip-to-wafer (MC2W) 3D stacking technologies based on via-last TSV integration. In this work, we verify the effectiveness of room-temperature CVD named OER (Ozone-Ethylene Radical generation)-TEOS-CVD® to deposit a TSV liner SiO 2 layer. The film quality including dielectric constants is evaluated alternative to plasma-enhanced (PE)-TEOS-CVD SiO 2 . In addition, solid-solid inter-diffusion bonding of 3-μm-thick Sn with 0.5-μm-thick Au is demonstrated to achieve multiple multichip bonding for retinal prosthesis system fabrication with a 3D artificial retina chip. Low-temperature bonding at 190°C is realized by the Au/Sn metallurgy. Good bondability is also obtained with the Au electrodes preliminarily exposed at high temperature. There are no Sn microbump extrusion, which is highly expected to be used for 3D-ICs with fine-pitch solder microbump interconnection.

Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion

3D IC Integration and 3D IC Packaging

This letter describes a direct Cu bonding technology to there-dimensionally integrate heterogeneous dielets based on a chip-on-wafer configuration. 100- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -cubed blue <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> LEDs temporarily adhered on a photosensitive resin are interconnected by semi-additive plating (SAP) without thermal compression bonding. By using SAP bonding, a lot of dielets can be stacked on thin 3D-IC chiplets. The following three key technologies are applied to solve the yield issues of SAP bonding. After pick-and-place assembly, additional coplanarity enhancement eliminates Cu bridges grown to a small gap between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> LEDs and photosensitive resin. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> LEDs arrays with sidewalls insulated by room-temperature ozone-ethylene-radical (OER)-SiO2-CVD are successfully bonded on sapphire wafers and a thin 3D-IC with through-Si via (TSV). Further design optimization is required, but partial seed pre-etching works well to increase the yield. Fully integrated module implementation with the 3D-ICs will be the next stage, however, we discuss a superior prospect for yield enhancement toward nearly 100%. 

/pdf/room-temperature-direct-cu-semi-additive-plating-sap-bonding-2wgokuir.pdf

Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED

High-density interconnections are highly required for 3D IC such as FPGA and image sensor applications. Fine-pitch interconnects using conventional solder microbumps are still required. To meet this requirements, low-height Cu/Sn microbumps are evaluated in this study. The thermal compression bonding with the low-height solder microbumps makes it challenging to fulfill high-viscous capillary underfill (CUF) into extremely small gaps between the chips stacked in layers. Here, we demonstrate to apply a 7-μm-thick non-conductive film (NCF) to flip-chip bonding with the low-height solder microbumps. Compared with a CUF, the electrical characterization such as electromigration (EM) and leakage current of microbump daisy chains with the ultra-thin NCF was investigated with temperature cycle test (TCT) and unbiased HAST.

7-μm-thick NCF technology with low-height solder microbump bonding for 3D integration

Impact of temporary bonding conditions and temporary adhesive properties on mechanical stresses in multichip thinning is evaluated for high-yield multichip-to-wafer (MC2W) heterogeneous 3D integration. It turned out that no sidewall covering of chips with a temporary adhesive gives low mechanical stress to the chip edge, leading to less chipping and cracking.

https://iopscience.iop.org/article/10.7567/1347-4065/ab4f3c/pdf

Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration

We have fabricated microbump daisy chains with a low-height solder thickness of 2.5 μm in order to evaluate flip-chip bonding capabilities. Electrical characteristics of the bonded microbumps in three-dimensionally stacked chips were compared between a very thin non-conductive film (NCF) and capillary underfill (CUF). The resulting I- V behaviors showed that the resistance of the daisy chain with the NCF was lower than that with the CUF, inDICating that the low-height solder microbumps with combination of the thin NCF can be a promising candidate for future fine-pitch inter-chip connection in 3DICs.

Rui Liang

Papers

7-μm-thick NCF technology with low-height solder microbump bonding for 3D integration

Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion

Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration

Characterization of Low-Height Solder Microbump Bonding for Fine-Pitch Inter-Chip Connection in 3DICs