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Proceedings ArticleDOI

7-μm-thick NCF technology with low-height solder microbump bonding for 3D integration

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TLDR
In this paper, the thermal compression bonding with the low-height solder microbumps makes it challenging to fulfill high-viscous capillary underfill (CUF) into extremely small gaps between the chips stacked in layers.
Abstract
High-density interconnections are highly required for 3D IC such as FPGA and image sensor applications. Fine-pitch interconnects using conventional solder microbumps are still required. To meet this requirements, low-height Cu/Sn microbumps are evaluated in this study. The thermal compression bonding with the low-height solder microbumps makes it challenging to fulfill high-viscous capillary underfill (CUF) into extremely small gaps between the chips stacked in layers. Here, we demonstrate to apply a 7-μm-thick non-conductive film (NCF) to flip-chip bonding with the low-height solder microbumps. Compared with a CUF, the electrical characterization such as electromigration (EM) and leakage current of microbump daisy chains with the ultra-thin NCF was investigated with temperature cycle test (TCT) and unbiased HAST.

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Citations
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Proceedings ArticleDOI

Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide Systems

TL;DR: In this paper , the authors studied the hybrid bonding process with a copper (Cu)/polyimide (PI) system by optimizing aqueous acid treatment, height control of Cu protrusion, and temporary/permanent bonding conditions for practical use.
Proceedings ArticleDOI

Cu-SiO2 Hybrid Bonding Yield Enhancement Through Cu Grain Enlargement

TL;DR: In this paper , the authors investigated the effect of an extremely large and relatively ordered Cu grains on the yield of Cu-Cu direct bonding/Cu-SiO2 hybrid bonding.
Proceedings ArticleDOI

Tight-Pitched 10 μm-Width Solder Joints for c-2-c and c-2-w 3D-Integration in NCF Environment

TL;DR: In this paper , the thermal and electrical stability of 10 µm-sized solder micro-joints fenced with nonconducting film (NCF) under tight pitch configuration has been studied for chip-to-chip and chip to wafer integaration via thermal cycle test and Kelvin measurement under constant current-stressing (CCS).
References
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Journal ArticleDOI

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

TL;DR: In this article, a 3D shared-memory test chip with three-stacked layers was fabricated by bonding the wafers with vertical buried interconnections after thinning.
Proceedings ArticleDOI

Advances in 3D CMOS sequential integration

TL;DR: In this article, a 3D sequential CMOS integration of top Si active layers is presented, and the electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm.
Proceedings ArticleDOI

Novel stacked CMOS image sensor with advanced Cu2Cu hybrid bonding

TL;DR: Wang et al. as mentioned in this paper have successfully mass-produced novel stacked back-illuminated CMOS image sensors (BI-CIS), which introduced advanced Cu2Cu hybrid bonding that had developed.
Journal ArticleDOI

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

TL;DR: The basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology.
Proceedings ArticleDOI

NCF for pre-applied process in higher density electronic package including 3D-package

TL;DR: In this paper, a novel non conductive film (NCF) support for the pre-applied process that connects and underfills a chip simultaneously was developed for higher density electronic package including 3D-package.
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