We have studied the hybrid bonding process with a copper (Cu)/polyimide (PI) system by optimizing aqueous acid treatment, height control of Cu protrusion, and temporary/permanent bonding conditions for practical use. The study found that the treatment with an aqueous solution of citric or ascorbic acid and 80 nm-protrusion contributed to the improvement in the bonding yield of Cu electrodes. The suitable temperature and pressure of the permanent bonding were determined at 250 °C and 5 MPa, and the mechanically tough junctions for both Cu-Cu and PI-PI interface were successfully achieved with relatively low resistance.

Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide Systems

We have investigated the effect of an extremely large and relatively ordered Cu grains on the yield of Cu-Cu direct bonding/Cu-SiO2 hybrid bonding. Both modified electroplating method and the post processing have resulted into the formation of 10 – 15 μm large Cu grains before Cu-Cu direct bonding/CuSiO2 hybrid bonding. Employing such large and oriented grains, we have successfully carried out Cu-SiO2 hybrid bonding using 5 μm-size Cu electrodes at 10 μm-pitch values. The microstructural evaluation confirmed the formation relatively oriented Cu-grains. The more tensile nature of oriented Cu grains formed by modified electroplating and post processing might facilitate the Cu diffusion during the Cu-Cu direct/Cu-SiO2hybrid bonding.

Cu-SiO2 Hybrid Bonding Yield Enhancement Through Cu Grain Enlargement

Mixed-signal 3D-ICs have a stacked structure of digital and analog circuit chips. In this study, the effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC. The noise propagation via through-silicon vias (TSVs) was measured, with a ring-oscillator as a noise source. For a comprehensive investigation, TSV-liner interface states were evaluated along the depth direction using unique multiwell-structured TSVs and a charge-pumping method. It was considered that the interface traps and nonconformal thickness of the TSV liner increased the noise propagation among stacked chips.

/pdf/investigation-of-tsv-liner-interface-with-multiwell-16pmnegnfl.pdf

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

In this paper, a novel through-silicon via (TSV) structure, named partial coaxial TSV (PC-TSV), is proposed to suppress TSV-induced substrate noise. In this structure, the via is surrounded by a benzocyclobutene (BCB) layer, and a grounded metal ring placed at one end. The BCB layer can effectively reduce the leakage of the signal to the substrate, and the metal ring provides a low impedance path for the substrate noise. An equivalent RLGC model of this structure is also established, and it is verified by simulated result from CST. Then, the performance of PC-TSV is compared with that of the traditional TSV, TSV with p+ layer, and TSV with p+ guard ring. Analysis results in frequency domain indicate PC-TSV has a larger $\vert \text{S}_{21}\vert $ and less near-end crosstalk than other three structures. Additionally, analysis results in time domain show that the substrate voltage noise of this structure is obviously reduced compared with the TSV with p+ layer and TSV with p+ guard ring. Also, a feasible process flow for this structure is given and it is simpler than that for traditional coaxial TSV.

/pdf/partial-coaxial-through-silicon-via-for-suppressing-the-1b8aac881f.pdf

Partial Coaxial Through-Silicon via for Suppressing the Substrate Noise in 3-Dimensional Integrated Circuit

Abstract The design of organic/inorganic nanoparticles hybrids provides the great potential for the fabrication of γ-ray sensor systems. Herein, structural and dosimetric properties of the gamma irradiated poly vinyl acetate (PVAc) doped with cadmium telluride quantum dots (CdTe QDs) and graphene oxide (GO) nanoflakes have been investigated. Thioglycolic acid (TGA) capped water-soluble CdTe QDs and (GO) nanoflakes are synthesized and characterized. Then, CdTe QDs/GO/PVAc sensors were formed by post-depositing CdTe and GO over polymer matrix. The photophysical interactions between nanoparticles and organic polymer have been investigated using ohmic contact detectors with two gold coated electrodes. Real time dose rate information of the sensors such as sensitivity, repeatability, and the linearity of dose rate response were assessed. A wider photoelectric response range and wider gamma harvesting range were observed in the resultant hybrid gamma sensor at a standard bias voltage with respect to non-hybrid CdTe QDs/PVAc sensors.

Cadmium telluride quantum dots/graphene oxide/poly vinyl acetate (CdTe QDs/GO/PVAc) nanocomposite. A novel sensor for real time gamma radiation detection

Through-silicon-via (TSV) with polymer liner has attracted considerable attention because a polymer liner has low dielectric constant and good step coverage along the TSV surface, and it can suppress the TSV-induced stress. A polyimide (PI) is used as the polymer liner of TSV. However, there is a modulation of the parasitic capacitance present between TSV metal and Si substrate due to its high polar character. Therefore, in this paper, we propose the deployment of benzocyclobutene (BCB) and polybenzoxazole (PBO) which consists of no-polar groups as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structures with PI, BCB or PBO liners were fabricated and evaluated. In the case of BCB and PBO liners, remarkable hysteresis suppressions of the C-V curves was observed as compared to that of the PI liner. These results indicate that polar character is one of the most important characters for suppression of the capacitance modulation around TSVs and the detrapped-charge-induced signal noise. Then, BCB and PBO is a promising liner material of TSV for realizing highperformance and high-reliability three-dimensional stacked ICs.

Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs

High-density interconnections are highly required for 3D IC such as FPGA and image sensor applications. Fine-pitch interconnects using conventional solder microbumps are still required. To meet this requirements, low-height Cu/Sn microbumps are evaluated in this study. The thermal compression bonding with the low-height solder microbumps makes it challenging to fulfill high-viscous capillary underfill (CUF) into extremely small gaps between the chips stacked in layers. Here, we demonstrate to apply a 7-μm-thick non-conductive film (NCF) to flip-chip bonding with the low-height solder microbumps. Compared with a CUF, the electrical characterization such as electromigration (EM) and leakage current of microbump daisy chains with the ultra-thin NCF was investigated with temperature cycle test (TCT) and unbiased HAST.

7-μm-thick NCF technology with low-height solder microbump bonding for 3D integration

This paper deals with multichip-to-wafer (MC2W) 3D stacking technologies based on via-last TSV integration. In this work, we verify the effectiveness of room-temperature CVD named OER (Ozone-Ethylene Radical generation)-TEOS-CVD® to deposit a TSV liner SiO 2 layer. The film quality including dielectric constants is evaluated alternative to plasma-enhanced (PE)-TEOS-CVD SiO 2 . In addition, solid-solid inter-diffusion bonding of 3-μm-thick Sn with 0.5-μm-thick Au is demonstrated to achieve multiple multichip bonding for retinal prosthesis system fabrication with a 3D artificial retina chip. Low-temperature bonding at 190°C is realized by the Au/Sn metallurgy. Good bondability is also obtained with the Au electrodes preliminarily exposed at high temperature. There are no Sn microbump extrusion, which is highly expected to be used for 3D-ICs with fine-pitch solder microbump interconnection.

Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion

Impact of temporary bonding conditions and temporary adhesive properties on mechanical stresses in multichip thinning is evaluated for high-yield multichip-to-wafer (MC2W) heterogeneous 3D integration. It turned out that no sidewall covering of chips with a temporary adhesive gives low mechanical stress to the chip edge, leading to less chipping and cracking.

https://iopscience.iop.org/article/10.7567/1347-4065/ab4f3c/pdf

Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration

We have fabricated a new 3D-IC embedded flexible hybrid system (FHS) based on a Fan-Out Wafer-Level Packaging (FOWLP). The unique FHS structure is consisting of PDMS as a flexible substrate in which the 3D-IC with through-Si vias (TSVs) and microbumps are embedded. The mechanical and electrical properties of the 3D-IC embedded FHS are characterized by using repeated bending test with the TSV/microbump daisy chains. The new FHS can be expected to be used as high-performance wearable device systems for biomedical applications.

Sungho Lee

Papers

Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs

7-μm-thick NCF technology with low-height solder microbump bonding for 3D integration

Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion

Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration

Development of 3D-IC Embedded Flexible Hybrid System