Showing papers by "Saibal Mukhopadhyay published in 2010"

An energy efficient cache design using spin torque transfer (STT) RAM

Abstract: The on-chip memory is a dominant source of power and energy consumption in modern and future processors This paper explores the use of a new emerging non-volatile memory technology as a replacement for SRAM based lower level caches - Spin Torque Transfer(STT) RAM While STTRAM achieves a reduction in leakage energy of 90% compared to SRAM, the dynamic energy for a write operation is 2X that of SRAM Consequently, we propose additional microarchitectural optimizations to reduce overall dynamic energy which achieve an average reduction in dynamic energy over the base case of 30% with a range of 16% to 60% across 10 benchmarks

Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system

Abstract: In this paper we present a test structure and design methodology for testing, characterization, and self-repair of TSVs in 3D ICs. The proposed structure can detect the signal degradation through TSVs due to resistive shorts and variations in TSV. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery circuit to improve signal fidelity. The paper presents the design of the test/recovery structure, the test methodologies, and demonstrates its effectiveness through stand alone simulations as well as in a full-chip physical design of a 3D IC.

A dynamic timing control technique utilizing time borrowing and clock stretching

Abstract: In this paper, a dynamic timing control technique employing a time-borrowing flip-flop with a time-borrowing detection and a clock shifter is presented to prevent timing errors of a system with a minimized performance penalty. The proposed flip-flop allows time borrowing during a time-borrowing window (TBW) on critical paths and generates a time-borrowing detection signal used by the clock shifter to stretch the clock period by TBW. This makes the system delay-error tolerant at a lower voltage or a higher frequency without any error management. To validate the proposed technique, we designed a prototype in a 180-nm CMOS technology. At a 10% activation probability of critical paths, the measurement results show a power reduction of up to 22% (at the same clock frequency) or an operating frequency increase of up to 10% (at the same power) compared to those of a conventional design.

On-chip Peltier cooling using current pulse

Abstract: Thermoelectric coolers (TECs) can address an efficient removal of localized heat for a wide range of applications such as microelectronic processors, DNA micro arrays, lasers. The efficient usage of thermoelectric devices for these applications require investigation and remedy of various obstacles such as integration of these devices with electronic package, parasitic contact resistances and utilization of appropriate current pulses and control algorithms. We investigate the effect of steady state and transient mode of operation of ultrathin TEC devices on hot spot temperature reduction on a chip through a developed computational model. The numerical model incorporates the effect of thermal and electrical contact resistances to analyze the hot spot cooling. Our analysis shows that transient pulses can be very effective to reduce the hotspot temperature in addition to the cooling achieved by the steady state current through the device. Thermal and electrical contact resistance play a very crucial role in the performance of TEC devices as high values of these resistances can completely diminish the effect of Peltier cooling. The effect of these parasitic resistances is even higher for the transient cooling of hot-spots by the pulsed current through the device compared to the steady state operation.

Self-Repairing SRAM Using On-Chip Detection and Compensation

Abstract: In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die V t variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose a closed-loop compensation scheme using on-chip monitors that directly sense the global read stability and writability of the cell. Simulations based on 45-nm partially depleted silicon-on-insulator technology demonstrate the viability and the effectiveness of the scheme in SRAM yield enhancement.

Thermoelectric Coolers for Thermal Gradient Management on Chip

Abstract: Site-specific and on-demand cooling of hot spots in the microprocessors can provide efficient cooling solution, improve its performance and increase its life time by reducing peak temperature and achieving more uniform thermal profile on the chip. Thermoelectric coolers (TEC) have the potential to provide such efficient cooling of hot spots on a chip. We investigate pulse cooling behavior of ultra-thin multiple TEC devices integrated inside the electronic package on the active side of a chip below the heat spreader. Various pulse profiles have been studied to obtain optimal shape of the current pulse in order to efficiently operate TECs considering crucial parameters such as the total energy consumed in TECs, peak temperature on the chip, temperature overshoot at hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be most effective with maximum cooling and half the energy expenditure in comparison to a constant current pulse. It has been observed that high thermal contact resistances can entirely negate the transient cooling effect of the TECs. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the temperature of the hot spots can be retained below a threshold using transient current pulses through the TECs. This underlines the benefits of using multiple TECs for hot spot cooling in order to obtain favorable thermal profile on the chip in an energy efficient way.Copyright © 2010 by ASME

Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes

Abstract: This brief analyzes the circuit-induced challenges to reliability and write current scaling of spin-torque-transfer random access memory (STTRAM). We show that, at sub-90-nm nodes, increased transistor leakage increases the probability of incorrect sensing requiring a higher read current. However, a higher read current can increase the read disturb failure, particularly with a reduced write current. To satisfy the conflicting requirements of read margin and sensing accuracy, we propose a source-line biasing technique. Simulations in predictive 65-nm nodes show that the proposed solution simultaneously reduce the sensing errors and improve the read margin.

Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration

Abstract: We present adaptive spatiotemporal power migration (ASTPM) for burn-in of many core chips. ASTPM adapts the number of simultaneously stressed cores and dynamically varies their location to prevent thermal runaway, improve test-quality, and optimize burn-in time.

Thermal mangament of multicore processors using power multiplexing

Abstract: One of the novel methods for the thermal management of multi-core processors is power multiplexing (also known as core hopping) which involves dynamical change of the locations of active cores within the chip at fixed time intervals. The power multiplexing technique helps in reducing the number of hotspots on the chip by providing a spatially uniform thermal profile which in turn lowers the maximum temperature rise on the chip. We quantify the effects of power multiplexing on the thermal profile of multi-core processor chip. Different core migration policies have been implemented in an attempt to evolve an optimally suitable policy for the multiplexing purpose. We observe that the selection of appropriate migration policy and the migration rate can efficiently reduce the spatial non-uniformity and peak temperature on the chip. The ratio of active to total cores has been varied to accommodate and analyze the effect of varying computing workload. We correlated the cooling power with the peak temperature on the chip and discussed the efficient usage of core-migration policies in the context of the power reduction.

A low power system with adaptive data compression for wireless monitoring of physiological signals and its application to wireless electroencephalography

Abstract: Remote wireless monitoring of physiological signals has emerged as a key enabler for biotelemetry and can significantly improve the delivery of healthcare. Improving the energy-efficiency and battery-lifetime of the monitoring units without sacrificing the acquired signal quality is a key challenge in large-scale deployment of bio-electronic systems for remote wireless monitoring. In this paper, we present a design methodology for low power wireless monitoring of Electroencephalography (EEG) data. The proposed design performs a real-time accuracy energy trade-off by controlling the volume of transmitted data based on the information content in the EEG signal. We consider the effect of different system parameters in order to design an optimal system. Our analysis shows that the proposed system design approach can provide significant savings in transmitter power with minimal impact on the monitored EEG signal accuracy. We analyze the impact of noise of the wireless channel and show that an adaptive compression system has better performance for BER ≪ 10−4.

Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study

Abstract: We present an accurate model of the self-heating effect in the Spin-Torque-Transfer RAM (STTRAM) using finite-volume-methods and thermal RC based compact models. We couple device level thermal simulation to the self-heating phenomenon to show that self-heating during write operation can result in significant temperature increase in STTRAM which in turn adversely affect the read disturb, leakage energy and sensing accuracy.

Signal processing methods and hardware-structure for on-line characterization of thermal gradients in many-core processors

Abstract: In this paper we propose a hardware-structure based on signal processing methods for on-line extraction of on-chip spatial and temporal thermal gradients in many-core chips. The proposed method uses digital filters to compute the magnitude of high-frequency variations in thermal fields and correlate that to thermal gradients. The functionality of the system is demonstrated using full-chip thermal simulation of a predictive 1024 core systems in 11nm nodes. The power and area of the structure is evaluated using post-layout simulations in predictive 45nm technology.