Said Hamdioui

TL;DR: This paper discusses and analyzes the main challenges and limitations of CMOS scaling, not only from physical and technological point of view, but also from material (e.g., high-k vs. low-k) and economical points of view as well.

TL;DR: In this paper, the authors provide a tutorial overview of recent efforts to develop computing systems based on spin waves instead of charges and voltages, and discuss the current status and challenges to combine spin-wave gates and obtain circuits and ultimately computing systems, considering essential aspects such as gate interconnection, logic level restoration, input output consistency, and fan-out achievement.

TL;DR: The paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability.

TL;DR: A new test is introduced, with a test length of 22n, that detects all realistic simple static faults in RAMs, because none of the current industrial march tests has the capability to detect all these faults.

TL;DR: The paper presents new memory tests derived to target the dynamic fault class, shown that conventional memory tests constructed to detect static faulty behavior of a specific defect do not necessarily detect the dynamic faulty behavior.