The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind. The emphasis is on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity. Topics covered includes an introduction to the concepts in cryptography, attacks against cryptographic systems, key use and handling, random bit generation, encryption modes, and message authentication codes. Recommendations on algorithms and further reading is given in the end of the paper. This paper should make the reader able to build, understand and evaluate system descriptions and designs based on the cryptographic components described in the paper.

[서평]「Applied Cryptography」

We present the theory and design of interval type-2 fuzzy logic systems (FLSs). We propose an efficient and simplified method to compute the input and antecedent operations for interval type-2 FLSs: one that is based on a general inference formula for them. We introduce the concept of upper and lower membership functions (MFs) and illustrate our efficient inference method for the case of Gaussian primary MFs. We also propose a method for designing an interval type-2 FLS in which we tune its parameters. Finally, we design type-2 FLSs to perform time-series forecasting when a nonstationary time-series is corrupted by additive noise where SNR is uncertain and demonstrate an improved performance over type-1 FLSs.

https://sipi.usc.edu/~mendel/publications/Liang%26Mendel%20TFS%2010-00%20%232.pdf

Interval type-2 fuzzy logic systems: theory and design

We introduce a type-2 fuzzy logic system (FLS), which can handle rule uncertainties. The implementation of this type-2 FLS involves the operations of fuzzification, inference, and output processing. We focus on "output processing," which consists of type reduction and defuzzification. Type-reduction methods are extended versions of type-1 defuzzification methods. Type reduction captures more information about rule uncertainties than does the defuzzified value (a crisp number), however, it is computationally intensive, except for interval type-2 fuzzy sets for which we provide a simple type-reduction computation procedure. We also apply a type-2 FLS to time-varying channel equalization and demonstrate that it provides better performance than a type-1 FLS and nearest neighbor classifier.

/pdf/type-2-fuzzy-logic-systems-20ss17tkqw.pdf

Type-2 fuzzy logic systems

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Design Of Analog Cmos Integrated Circuits

Introduction to Mathematical Statistics. By R.V. Hogg and A. T. Craig. Pp. ix, 245. 47s. 1959. (The Macmillan Company, New York)

This paper discusses a novel, reduced complexity implementation of the Partial Transmit Sequence technique (PTS) for reducing the Peak to Average Power Ratio (PAPR) of OFDM signals. The original PTS provides good PAPR reduction at the cost of computational complexity. The use of large number of IFFT blocks in PTS has been replaced by a single IFFT block. The parallel processing of the PTSs has been replaced by serial processing. Reducing the number of IFFT blocks and replacing parallel processing by serial processing reduces the computational complexity. The simulation results demonstrate that the proposed technique provides performance as good as standard PTS.

Single IFFT block based reduced complexity Partial Transmit Sequence technique for PAPR reduction in OFDM

The ZigBee standard is based on the application for IEEE 802.15.4 LR WPAN for control and monitoring of wireless sensor network, short range low data rate wireless communication system. the ZigBee standard along with IEEE 802.15.4 standard combined together to form complete ZigBee networking protocol.the physical layer and MAC layer are are defined by IEEE 802.15.4, and other upper layers like network layer, application layer etc are defined by ZigBee standard. ZigBee is particularly designed for low power short range wireless communication system. The work presented in this paper is the design and implementation of ZigBee baseband transceiver for IEEE 802.15.4. The design includes the spread spectrum of the input data bit ‘0’ and ‘1’ according to the quasi orthogonal symbol to chip mapping employed in standard IEEE 802.15.4. The unipolar input data bits ‘0’ and ‘1’ are transmitted with out converting to bipolar signal. The spreading method Direct sequence spread spectrum are implemented in the design of the transceiver, and later the design includes Offset Quadrature phase shift keying modulation with half sine pulse shaping. Half sine pulse shaping is done to reduce Inter symbol Interference.The design is carried out by the hardware description language Verilog HDL and implemented in the VIRTEX 5 FPGA board. The analog continuous sample values used in the design are stored in the memory of the board and used as per the clock signal. The simulation of the design is done by the help of Mentor Graphics Modelsim simulator and the synthesis is done by XILINX ISE SYNTHESIZER.

FPGA Implementation of ZigBee Baseband Transceiver System for IEEE 802.15.4

In this paper, we explore the issue of connection provisioning and performance analysis in WDM network ensuring the QoS requirement of the connection requests from the client in the network Each connection request can be specified with a Q-Factor requirement which is defined in terms of bandwidth and delay associated with the light path The paper discusses the improvement in blocking probably for incoming requests while performing routing by proposed algorithm and the traditional shortest path algorithm

/pdf/qos-based-light-path-provisioning-and-performance-analysis-3ujwf8ztk7.pdf

QoS based light path provisioning and performance analysis in WDM network

This paper presents an extensive overview of the existing techniques in adaptive channel equalisation. It also introduces high performance adaptive equaliser structures using ANN. Extensive computer simulations have been carried out to show performance superiority of the ANN equalisers over the conventional equalisers. The neural algorithms used for training are, Back Propagation (BP), Improved Back Propagation (IBP) and Single Neuron Algorithm (SNA). The IBP algorithm proposed by the authors offers the least steady state Mean Square Error (MSE) compared to BP algorithm with no additional computational burden. Further the SNA equaliser developed in this paper is a real time implementable structure which involves minimum computation while yields performance close to the BP algorithm.

Development of New Neural Adaptive Equalisers and their Performance Comparison with Existing Techniques

The Cloud RAN(C-RAN) is an innovative network solution for the 5th generation wireless communication (5G). This centralized architecture split the traditional RAN architecture into a remote unit known as Remote Radio Head (RRH) and a Centralized Baseband Unit (C-BBU). Both the C-BBU and RRH are connected through optical fiber links. The improper placement of the C-BBU other than the centralized location leads to increase of parameters like network transport delay (Td) and total link cost (Lc). In this paper we proposed the k-mean algorithm to find out the optimal centroid position in the cellular cluster for placement of C-BBU. To find out the total Td and Lc of each and every link of the C-RAN networks, optical link budget analysis is carried out. The above mention two steps mostly help the network service providers to localize the C-BBU and to estimate the total cost and network delay incur during the network design.

Sarat Kumar Patra

Papers

Single IFFT block based reduced complexity Partial Transmit Sequence technique for PAPR reduction in OFDM

FPGA Implementation of ZigBee Baseband Transceiver System for IEEE 802.15.4

QoS based light path provisioning and performance analysis in WDM network

Development of New Neural Adaptive Equalisers and their Performance Comparison with Existing Techniques

Optimal Placement of Centralized BBU (C-BBU) for Fronthaul and Backhaul Optimization in Cloud-RAN Network