Power Aware Testing And Test Strategies For Low Power Devices

The security of logic locking has been called into question by various attacks, especially a Boolean satisfiability (SAT) based attack, that exploits scan access in a working chip. Among other techniques, a robust design-for-security (DFS) architecture was presented to restrict any unauthorized scan access, thereby, thwarting the SAT attack (or any other attack that relies on scan access). Nevertheless, in this work, we successfully break this technique by recovering the secret key despite the lack of scan access. Our security analysis on a few benchmark circuits protected by the robust DFS architecture demonstrates the effectiveness of our attack; on average ∼95% of the key bits are correctly recovered, and almost 100% in most cases. To overcome this and other prevailing attacks, we propose a defense by making fundamental changes to the robust DFS technique; the new defense can withstand all logic locking attacks. We observe, on average, lower area overhead (∼1.65%) than the robust DFS design (∼5.15%), and similar test coverage (∼99.88%).

Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access

The security of logic locking has been called into question by various attacks, especially a Boolean satisfiability (SAT) based attack, that exploits scan access in a working chip. Among other techniques, a robust design-for-security (DFS) architecture was presented to restrict any unauthorized scan access, thereby, thwarting the SAT attack (or any other attack that relies on scan access). Nevertheless, in this work, we successfully break this technique by recovering the secret key despite the lack of scan access. Our security analysis on a few benchmark circuits protected by the robust DFS architecture demonstrates the effectiveness of our attack; on average ~95% of the key bits are correctly recovered, and almost 100% in most cases. To overcome this and other prevailing attacks, we propose a defense by making fundamental changes to the robust DFS technique; the new defense can withstand all logic locking attacks. We observe, on average, lower area overhead (~1.65%) than the robust DFS design (~5.15%), and similar test coverage (~99.88%).

Scan design is a widely used design-for-test methodology since it enhances the controllability and observability of integrated circuits significantly. However, it may become a channel to leak secret information and, hence, threatens the hardware security seriously. In this paper, a secure scan test scheme is presented to thwart all the existing scan-based noninvasive attacks. On one hand, the proposed scheme keeps isolating the cipher key when the crypto chip runs in the test mode. In this period, the data shifted out from scan chains are not related to the cipher key. On the other hand, if the crypto chip first enters the functional mode after power-ON or reset, the switching from the functional mode to the test mode is prohibited. Consequently, the intermediate sensitive data stored in scan chains are protected. The presented scheme allows performing all sorts of tests, such as stuck-at test and delay test with a simple modification, and it maintains the advantages of scan design. Furthermore, it incurs minimal area overhead while protecting powerfully a crypto chip.

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A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks

Scan-based side-channel attacks have been gaining a prominence among the malicious attackers. The unprotected scan chains are extremely vulnerable and could be exploited to extract the secret information from a security chip such as an Advanced Encryption Standard (AES) cryptochip. To protect the secret information from being hacked it is utmost necessary to redesign the scan chain with security features. In this paper, we propose a secure scan architecture aiming at the protection of AES cryptochips against scan-based attacks. The proposed idea is based on the principle of test pattern encryption. The major contribution of our architecture is area efficiency and its security features without hampering test, diagnose, and debug capability of the original scan chain. The experimental results and security analysis shows the efficacy of proposed design.

On Securing Scan Design Through Test Vector Encryption

Almost every complex circuit today employs scan-based Design-for-Testability (DFT) architecture to enhance controllability and observability for every flip-flop in the design, thereby improve the testability. However, the DFT structure can also be exploited to mount side-channel attacks to retrieve the secret key stored in a cryptographic chip, thus compromising its security. In this paper, we propose a new secure scan test architecture which isolates the encryption key whenever the cryptographic chip is switched to test mode. The encryption key remains isolated during the whole scan test process. It also clears the last functional states of the security sensitive scan cells as soon as the scan test mode is activated. The proposed secure scan test approach is capable of exercising all kinds of conventional stuck-at and timing test. The proposed approach has minimal hardware overhead and it is capable of preventing existing scan-based side channel attacks.

An efficient test technique to prevent scan-based side-channel attacks

Test and diagnosis requirements has made the use of scan design unavoidable for present day highly complex circuits However, scan design can be exploited to retrieve the secret information stored on a crypto chip by mounting scan based side channel attack The scan design poses a threat to the security of crypto chips as it gives the user the capability to control/observe the circuit state In this paper, we propose a technique to secure the scan design that can effectively defend the crypto chips against scan based side-channel attacks To use the scan architecture the user first needs to supply the test authorization key Once the user is authorized, the conventional test sequence can be started Furthermore, the proposed technique allows using the original test set without any test time and test data overhead In addition to that, the proposed technique leaves the debug capability intact and has a marginal area overhead

On Securing Scan Design from Scan-Based Side-Channel Attacks

Scan based diagnosis plays a critical role in yield enhancement of sub-nanometer technology based chips However, the scan chain itself can be subject to defects due to the large logic circuitry associated with it which constitute a significant fraction of total chip area In some cases, it has been observed that scan chain failures may account for 30% to 50% of chip failures Hence, scan chain testing and diagnosis has become very crucial in recent years In this paper, we propose a hardware-assisted low cost and low complexity scan chain diagnosis technique The proposed technique is very simple in operation and provides maximum resolution for stuck-at fault diagnosis

A low cost technique for scan chain diagnosis

Over the years, serial scan design has become the de-facto design for testability technique. The ease of testing and high test coverage has made it gain widespread industrial acceptance. However, there are penalties associated with the serial scan design. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today’s very high-speed designs with minimum possible combinational depth, the performance degradation caused by the scan multiplexer has become magnified. Hence, to maintain circuit performance, the timing overhead of scan design must be addressed. In this paper, we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer from the functional path. The proposed design can help improve the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in the “mixed scan” test wherein it can be used as a serial scan cell as well as a random access scan (RAS) cell. The mixed scan test architecture has been implemented using the proposed scan flip-flop. The experimental results show a promising reduction in interconnect wire length, test time, and test data volume, compared to the state-of-the-art RAS and multiple serial scan implementations.

Satyadev Ahlawat

Papers

On Securing Scan Design Through Test Vector Encryption

An efficient test technique to prevent scan-based side-channel attacks

On Securing Scan Design from Scan-Based Side-Channel Attacks

A low cost technique for scan chain diagnosis

A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test