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Scott A. Bell
Researcher at Advanced Micro Devices
Publications - 87
Citations - 2278
Scott A. Bell is an academic researcher from Advanced Micro Devices. The author has contributed to research in topics: Layer (electronics) & Photoresist. The author has an hindex of 25, co-authored 87 publications receiving 2242 citations. Previous affiliations of Scott A. Bell include GlobalFoundries.
Papers
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Proceedings ArticleDOI
FinFET scaling to 10 nm gate length
Bin Yu,Leland Chang,Shibly S. Ahmed,Haihong Wang,Scott A. Bell,Chih-Yuh Yang,Cyrus E. Tabery,Chau M. Ho,Qi Xiang,Tsu-Jae King,Jeffrey Bokor,Chenming Hu,Ming-Ren Lin,D. Kyser +13 more
TL;DR: In this paper, the authors report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm.
Patent
Process for fabricating a semiconductor device component using a selective silicidation reaction
TL;DR: In this paper, a process for fabricating a semiconductor device includes the formation of a hard mask using lithographic techniques followed by a selective silicidation reaction process to reduce the lateral dimension of the hard mask.
Patent
Bi-layer trim etch process to form integrated circuit gate structures
TL;DR: In this paper, a bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, patterning the imaging layer, selectively trim etching the organic under-layer to form a pattern, and removing portions of the poly-silicon layer using the pattern formed from the removed portions of organic under layer.
Patent
Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning
Philip A. Fisher,Marina V. Plat,Chih-Yuh Yang,Christopher F. Lyons,Scott A. Bell,Douglas J. Bonser,Lu You,Srikanteswara Dakshina-Murthy +7 more
TL;DR: In this article, a method for the use of an amorphous carbon anti-reflective coating mask for an integrated circuit is described, where a layer of conductive material is added to the layer of carbon and an anti reflective coating (ARC) layer is added over the carbon.
Patent
Method of forming sub-lithographic spaces between polysilicon lines
TL;DR: In this paper, a method of forming spaces between polysilicon lines can include patterning structures having top SiON layers and bottom amorphous carbon layers where the structures are located over a poly-silicon layer and are separated by a first width.