An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/μm) at a low operating voltage of 0.5 V. The nanotube transistor exhibits an impressively small inverse subthreshold slope of 94 mV/decade-nearly half of the value expected from a previous theoretical study. Numerical simulations show the critical role of the metal-CNT contacts in determining the performance of sub-10 nm channel length transistors, signifying the need for more accurate theoretical modeling of transport between the metal and nanotube. The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies.

Sub-10 nm carbon nanotube transistor.

Rise of silicene: A competitive 2D material

The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Tri-gate devices and methods of fabrication

High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

http://science.sciencemag.org/content/sci/355/6322/271.full.pdf

Scaling carbon nanotube complementary transistors to 5-nm gate lengths

While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm These MOSFETs are believed to be the smallest double-gate transistors ever fabricated Excellent short-channel performance is observed in devices with a wide range of gate lengths (10/spl sim/105 nm) The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs Due to the [110] channel crystal orientation, hole mobility in the fabricated p-channel FinFET exceeds greatly that in a traditional planar MOSFET At 105 nm gate length, the p-channel FinFET shows a record-high transconductance of 633 /spl mu/S//spl mu/m at a V/sub dd/ of 12 V Working CMOS FinFET inverters are also demonstrated

/pdf/finfet-scaling-to-10-nm-gate-length-2bejw0rpgu.pdf

FinFET scaling to 10 nm gate length

A semiconductor device (100) may include a substrate (110) and an insulating layer (120) formed on the substrate (110). A fin (210) may be formed on the insulating layer (120) and may include a number of side surfaces and a top surface. A first gate (410) may be formed on the insulating layer (120) proximate to one of the number of side surfaces of the fin (210). A second gate (420) and may be formed on the insulating layer (120) separate from the first gate (410) and proximate to another one of number of side surfaces of the fin (210).

Double gate semiconductor device having separate gates

A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

https://www.amrita.edu/system/files/publications/multi-step-chemical-mechanical-polishing-of-a-gate-area-in-a-finfet.pdf

Multi-step chemical mechanical polishing of a gate area in a FinFET

Strained Si NMOS transistors with Lgate down to 35 nm were fabricated using NiSi as a metal gate electrode material for the first time. Compared to poly gate devices, NiSi metal gate devices showed further enhanced performance with good control of short channel effects and no degradation in gate oxide integrity.

Strained silicon NMOS with nickel-silicide metal gate

A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.

Shibly S. Ahmed

Papers

FinFET scaling to 10 nm gate length

Double gate semiconductor device having separate gates

Multi-step chemical mechanical polishing of a gate area in a FinFET

Strained silicon NMOS with nickel-silicide metal gate

Systems and methods for forming dense n-channel and p-channel fins using shadow implanting