Engineering related research, such as research on worst-case execution time, uses experimentation to evaluate ideas. For these experiments we need example programs. Furthermore, to make the research experimentation repeatable those programs shall be made publicly available.

We collected open-source programs, adapted them to a common coding style, and provide the collection in open-source. The benchmark collection is called TACLeBench and is available from GitHub in version 1.9 at the publication date of this paper. One of the main features of TACLeBench is that all programs are self-contained without any dependencies on standard libraries or an operating system.

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TACLeBench: a benchmark collection to support worst-case execution time research

This survey provides an overview of the scientific literature on timing verification techniques for multi-core real-time systems. It reviews the key results in the field from its origins around 2006 to the latest research published up to the end of 2018. The survey highlights the key issues involved in providing guarantees of timing correctness for multi-core systems. A detailed review is provided covering four main categories: full integration, temporal isolation, integrating interference effects into schedulability analysis, and mapping and allocation. The survey concludes with a discussion of the advantages and disadvantages of these different approaches, identifying open issues, key challenges, and possible directions for future research.

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A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

Current processors provide high average-case performance, as they are optimized for general purpose computing. However, those optimizations often lead to a high worst-case execution time (WCET). WCET analysis tools model the architectural features that increase average-case performance. To keep analysis complexity manageable, those models need to abstract from implementation details. This abstraction further increases the WCET bound. This paper presents a way out of this dilemma: a processor designed for real-time systems. We design and optimize a processor, called Patmos, for low WCET bounds rather than for high average-case performance. Patmos is a dual-issue, statically scheduled RISC processor. A method cache serves as the cache for the instructions and a split cache organization simplifies the WCET analysis of the data cache. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average-case performance.

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Patmos: a time-predictable microprocessor

Timing compositionality is assumed by almost all multicore timing analyses. In this paper, we show that compositional timing analysis can be incorrect even for simple microarchitectures with in-order execution. We then introduce three approaches to enable sound compositional analysis: two based on analysis and one based on a hardware modification. In the experimental evaluation we explore the strengths and weaknesses of these three approaches. One of the two analysis-based approaches provides an attractive trade-off between analysis cost and precision, enabling sound compositional timing analysis even for microarchitectures with out-of-order execution.

Enabling Compositionality for Multicore Timing Analysis

MultiPARTES: Multi-core partitioning and virtualization for easing the certification of mixed-criticality systems

Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding.The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST.

T-crest

Deciding if an OSS project meets the required standards for adoption is hard, and keeping up-to-date with a rapidly evolving project is even harder Making decisions about quality and adoption involves analysing code, documentation, online discussions, and issue trackers There is too much information to process manually and it is common that uninformed decisions have to be made with detrimental effects CROSSMINER aims to remedy this by automatically extracting the required knowledge and injecting it into the developers’ Integrated Development Environments (IDE), at the time they need it to make design decisions This allows them to reduce their effort in knowledge acquisition and to increase the quality of their code CROSSMINER uniquely combines advanced software project analyses with online IDE monitoring Developers will be monitored to infer which information is timely, based on readily available knowledge stored earlier by a set of advanced offline deep analyses of related OSS projects

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Developer-Centric Knowledge Mining from Large Open-Source Software Repositories (CROSSMINER)

HIJA is an undertaking to create the technology conditions that will allow architecture neutrality for real-time systems (ANRTS). This paper makes the point that technology features are needed at both the execution level (platform) and the software engineering level (process). In order to cope with the wide range of real-time and embedded systems, 3 run-time profiles based on RTSJ are identified, the hard real-time Java profile, the soft real-time Java profile and the flexible real-time Java profile. These profiles also provide support for distributed applications based on both synchronous and asynchronous communication methods. In order to ensure that executing applications are functionally correct and satisfy resource constraints, a required tool set is described, including analysis tools for schedule-ability or functional correctness verification. Finally, results from a proof-of-concept implementation of ANRTS platforms and tool set, and their use for three different applications (avionics, automotive telematics, ambient system) are reported, confirming the feasibility of the ANRTS approach.

ANRTS platforms

The MedSecurance project focus on identifying new challenges in cyber security with focus on hardware and software medical devices in the context of emerging healthcare architectures. In addition, the project will review best practice and identify gaps in the guidance, particularly the guidance stipulated by the medical device regulation and directives. Finally, the project will develop comprehensive methodology and tooling for the engineering of trustworthy networks of inter-operating medical devices, that shall have security-for-safety by design, with a strategy for device certification and certifiable dynamic network composition, ensuring that patient safety is safeguarded from malicious cyber actors and technology "accidents".

Scott Hansen

Papers

T-crest

Developer-Centric Knowledge Mining from Large Open-Source Software Repositories (CROSSMINER)

ANRTS platforms

MedSecurance Project: Advanced Security-for-Safety Assurance for Medical Device IoT (IoMT)