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Wolfgang Puffitsch
Researcher at Technical University of Denmark
Publications - 39
Citations - 998
Wolfgang Puffitsch is an academic researcher from Technical University of Denmark. The author has contributed to research in topics: Cache & Garbage collection. The author has an hindex of 17, co-authored 39 publications receiving 906 citations. Previous affiliations of Wolfgang Puffitsch include Vienna University of Technology & University of Copenhagen.
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Journal ArticleDOI
T-crest
Martin Schoeberl,Sahar Abbaspour,Benny Akesson,Neil Audsley,Raffaele Capasso,Jamie Garside,Kees Goossens,Sven Goossens,Scott Hansen,Reinhold Heckmann,Stefan Hepp,Benedikt Huber,Alexander Jordan,Evangelia Kasapaki,Jens Knoop,Yonghui Li,Daniel Prokesch,Wolfgang Puffitsch,Peter Puschner,Andre Rocha,Claudio Silva,Jens Sparsø,Alessandro Tocchi +22 more
TL;DR: Within the T-CREST project the authors propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time.
Proceedings ArticleDOI
TACLeBench: a benchmark collection to support worst-case execution time research
Heiko Falk,Sebastian Altmeyer,Peter Hellinckx,Björn Lisper,Wolfgang Puffitsch,Christine Rochange,Martin Schoeberl,Rasmus Bo Sørensen,Peter Wägemann,Simon Wegener +9 more
TL;DR: Open-source programs are collected, adapted to a common coding style, and provided in open-source, with the main features of TACLeBench, which is that all programs are self-contained without any dependencies on standard libraries or an operating system.
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Martin Schoeberl,Pascal Schleuniger,Wolfgang Puffitsch,Florian Brandner,Christian W. Probst,Sven Karlsson,Tommy Thorn +6 more
TL;DR: This paper presents Patmos, a processor optimized for low WCET bounds rather than high average case performance, a dual- issue, statically scheduled RISC processor that relies on a customized compiler.
Predictable Flight Management System Implementation on a Multicore Processor
Guy Durrieu,Madeleine Faugere,Sylvain Girbal,Daniel Gracia Perez,Claire Pagetti,Wolfgang Puffitsch +5 more
TL;DR: This paper presents an approach for hosting a representative avionic function on a distributed-memory mul-ticore COTS architecture developed in collaboration by Thales and ONERA in order to improve the performance of the function while enforcing its predictability.
Journal ArticleDOI
Patmos: a time-predictable microprocessor
TL;DR: This paper designs and optimize a processor, called Patmos, for low WCET bounds rather than for high average-case performance, a way out of this dilemma: a processor designed for real-time systems.