This document provides updates to IEEE Std 802.16's MIB for the MAC, PHY and asso- ciated management procedures in order to accommodate recent extensions to the standard.

IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed Broadband Wireless Access Systems Draft Amendment: Management Information Base Extensions

Turbo equalization is an iterative equalization and decoding technique that can achieve equally impressive performance gains for communication systems that send digital data over channels that require equalization, i.e., those that suffer from intersymbol interference (ISI). In this article, we discuss the turbo equalization approach to coded data transmission over ISI channels, with emphasis on the basic ideas and some of the practical details. The original system introduced by Douillard et al. can be viewed as an extension of the turbo decoding algorithm by considering the effect of the ISI channel as another form of error protection, i.e., as a rate-1 convolutional code.

Turbo equalization

In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is accompanied by rigorous analysis for each key concept. The analysis ranges from the circuit to the micro-architectural level, and reference is given to process, physical and system levels when necessary. Among the main goals of this paper, it is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect. Accordingly, common misconceptions in the ULP domain are debunked and replaced with technically sound explanations.

Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold (NT) operation can achieve higher energy efficiency, and the performance scalability can be gained through parallelism. In this paper, we describe the design of an open-source RISC-V processor core specifically designed for NT operation in tightly coupled multicore clusters. We introduce instruction extensions and microarchitectural optimizations to increase the computational density and to minimize the pressure toward the shared-memory hierarchy. For typical data-intensive sensor processing workloads, the proposed core is, on average, $3.5\times $ faster and $3.2\times $ more energy efficient, thanks to a smart L0 buffer to reduce cache access contentions and support for compressed instructions. Single Instruction Multiple Data extensions, such as dot products, and a built-in L0 storage further reduce the shared-memory accesses by $8\times $ reducing contentions by $3.2\times $ . With four NT-optimized cores, the cluster is operational from 0.6 to 1.2 V, achieving a peak efficiency of 67 MOPS/mW in a low-cost 65-nm bulk CMOS technology. In a low-power 28-nm FD-SOI process, a peak efficiency of 193 MOPS/mW (40 MHz and 1 mW) can be achieved.

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

A method and system for storage and retrieval of blockchains with Galois Fields. One or more blocks for a blockchain are securely stored and retrieved with a modified Galois Fields on a cloud or peer-to-peer (P2P) communications network. The modified Galois Field provides at least additional layers for security and privacy for blockchains. The blocks and blockchains are securely stored and retrieved for cryptocurrency transactions including, but not limited to, BITCOIN transactions and other cryptocurrency transactions.

Method and system for storage and retrieval of blockchain blocks using galois fields

Battery life specifications drive the power consumption requirements of integrated circuits in implantable, wearable, and portable medical devices. In this paper, we present an embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption. Ultra-low-power operation is achieved via 0.5-1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

Microwatt Embedded Processor Platform for Medical System-on-Chip Applications

A medical system-on-chip (SoC) that integrates an ARM Cortex-M3 processor is presented. Ultra-low power operation is achieved via 0.5–1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.

Microwatt embedded processor platform for medical system-on-chip applications

In this paper, we present energy-efficient soft error (SE)-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs an low-complexity estimator of a main DSP block to guarantee reliability in presence of soft errors either in the MDSP or the estimator. For FIR filtering, it is shown that the proposed technique provides robustness to soft error rates of up to P/sub er/=10/sup -2/ in single-event upset (SEU). It is also shown that the proposed techniques provide 40%/spl sim/61% savings in power dissipation over that achieved via triple modula redundancy (TMR) when the desired signal-to-noise ratio SNR/sub des/=25/spl sim/35 dB.

Energy-efficient soft error-tolerant digital signal processing

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In this paper, we present block-interleaved pipelining (BIP) as a new high-throughput technique for MAP decoders. An area-efficient symbol-based BIP MAP decoder architecture is proposed by combining BIP with the well-known look-ahead computation. These architectures are compared with conventional parallel architectures in terms of speed-up, memory and logic complexity, and area. Compared to the parallel architecture, the BIP architecture provides the same speed-up with a reduction in logic complexity by a factor of M, where M is the level of parallelism. The symbol-based architecture provides a speed-up in the range from 1 to 2 with a logic complexity that grows exponentially with M and a state metric storage requirement that is reduced by a factor of M as compared to a parallel architecture. The symbol-based BIP architecture provides speed-up in the range M to 2M with an exponentially higher logic complexity and a reduced memory complexity compared to a parallel architecture. These high-throughput architectures are synthesized in a 2.5-V 0.25-/spl mu/m CMOS standard cell library and post-layout simulations are conducted. For turbo decoder applications, we find that the BIP architecture provides a throughput gain of 1.96 at the cost of 63% area overhead. For turbo equalizer applications, the symbol-based BIP architecture enables us to achieve a throughput gain of 1.79 with an area savings of 25%.

/pdf/area-efficient-high-throughput-map-decoder-architectures-4tll0egb81.pdf

Area-efficient high-throughput MAP decoder architectures

In this paper, two analytical methods are presented to investigate the soft information evolution characteristics of a soft-input soft-output (SISO) linear equalizer and its application to the design of turbo equalization systems without the reliance on extensive simulation. Given the channel and a SISO equalization algorithm, one method explored is to analytically compute the bit-error rate (BER) of the SISO equalizer in two extreme cases (no and perfect a priori information) from which a BER transfer characteristic is estimated. The second approach is to compute the mutual information [a key parameter of the extrinsic information transfer (EXIT) chart] at the two end points of the EXIT function. Then, by modeling the SISO equalizer BER transfer and EXIT functions as linear, some of the behavior of linear turbo equalization, such as how the BER performance can be improved as iterations proceed, can be predicted. Further, soft information evolution characteristics of different linear SISO equalizers can be compared and the usefulness of iterative methods such as linear turbo equalization for a given channel can be determined. Compared with existing methods for generating EXIT functions, these predictive methods provide insight into the iterative behavior of linear turbo equalizers with substantial reduction in numerical complexity.

/pdf/linear-turbo-equalization-analysis-via-ber-transfer-and-exit-5f74mhbh4o.pdf

Seok-jun Lee

Papers

Microwatt Embedded Processor Platform for Medical System-on-Chip Applications

Microwatt embedded processor platform for medical system-on-chip applications

Energy-efficient soft error-tolerant digital signal processing

Area-efficient high-throughput MAP decoder architectures

Linear turbo equalization analysis via BER transfer and EXIT charts