Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells

Quantum-dot Cellular Automata (QCA) is attracting a lot of attentions due to its extremely small feature sizes and ultra low power consumption. Up to now several designs using QCA technology have been proposed. However, we found not all of the designs function properly. Further, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing a large scale circuits using QCA technology an extremely time-consuming process. In this paper we show several critical vulnerabilities in the structures of primitive QCA gates and QCA interconnects, and propose a disciplinary guideline to prevent any additional plausible but malfunctioning QCA designs.

Quantum-dot Cellular Automata Design Guideline

An optimal design of full adder based on 5-input majority gate in coplanar quantum-dot cellular automata

Quantum dot-cellular automata (QCA) are one of novel emerging nanotechnology, which seem to be excellent alternatives to the conventional complementary metal-oxide semiconductor (CMOS) technology. QCA technology has a wide range of optimize facet such as ultra-low power consumption, faster switching speed and extremely density structure. In this paper, a novel exclusive-OR (XOR) gate is presented. This proposed XOR gate requires only 12 cells and dissipates 12.11 meV energies at 1.0Ek tunneling energy level. To inspect the efficacy of proposed XOR gate, new QCA design of half and full subtractor is introduced here. In comparison with previous QCA designs, the proposed layouts are implemented with the minimum area, minimum number of cells and delay without any wire-crossing techniques. The proposed, half and full subtractors require 19 and 32 cells and occupy 0.0186 μm2 and 0.0287 μm2 area respectively. To validate the accuracy of the proposed design, QCADesigner, a familiar QCA simulation tool is employed.

A novel 3-input XOR function implementation in quantum dot-cellular automata with energy dissipation analysis

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of $$0.02\,\upmu \hbox {m}^{2}$$0.02μm2 and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.

A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis

Designing efficient QCA logical circuits with power dissipation analysis

Towards ultra-efficient QCA reversible circuits

A Generative Adversarial Network (GAN) is an adversarial learning approach which empowers conventional deep learning methods by alleviating the demands of massive labeled datasets. However, GAN training can be computationally-intensive limiting its feasibility in resource-limited edge devices. In this paper, we propose an approximate GAN (ApGAN) for accelerating GANs from both algorithm and hardware implementation perspectives. First, inspired by the binary pattern feature extraction method along with binarized representation entropy, the existing Deep Convolutional GAN (DCGAN) algorithm is modified by binarizing the weights for a specific portion of layers within both the generator and discriminator models. Further reduction in storage and computation resources is achieved by leveraging a novel hardware-configurable in-memory addition scheme, which can operate in the accurate and approximate modes. Finally, a memristor-based processing-in-memory accelerator for ApGAN is developed. The performance of the ApGAN accelerator on different data-sets such as Fashion-MNIST, CIFAR-10, STL-10, and celeb-A is evaluated and compared with recent GAN accelerator designs. With almost the same Inception Score (IS) to the baseline GAN, the ApGAN accelerator can increase the energy-efficiency by $\sim 28.6\times$ ∼ 28 . 6 × achieving 35-fold speedup compared with a baseline GPU platform. Additionally, it shows 2.5× and 5.8× higher energy-efficiency and speedup over CMOS-ASIC accelerator subject to an 11 percent reduction in IS.

/pdf/apgan-approximate-gan-for-robust-low-energy-learning-from-cwycaouc8w.pdf

ApGAN: Approximate GAN for Robust Low Energy Learning From Imprecise Components

Designing High Speed Sequential Circuits by Quantum-Dot Cellular Automata: Memory Cell and Counter Study

In this paper, a probabilistic interpolation recoder (PIR) circuit is developed for deep belief networks (DBNs) with probabilistic spin logic (p-bit)-based neurons. To verify the functionality and evaluate the performance of the PIRs, we have implemented a $784 \times 200 \times 10$ DBN circuit in SPICE for a pattern recognition application using the MNIST dataset. The PIR circuits are leveraged in the last hidden layer to interpolate the probabilistic output of the neurons, which are representing different output classes, through sampling the p-bit's output values and then counting them in a defined sampling time window.The PIR circuit is proposed as an alternative for conventional interpolation methods which were based on using a resistor-capacitor tank to integrate each neuron's output, followed by an analog-to-digital converter to generate the digital output. The circuit simulation results of PIR circuit exhibit at least 43%, 66%,and 70% reductions in power, energy, and energy-error-product,respectively, compared to previous techniques, without using any of the area-consuming analog components in the interpolation circuit. In addition, the PIR circuits have an inherent single stuck-at fault tolerant features to tolerate either transient or permanent faults at the circuit's output. Reliability properties of the PIR circuits for single stuck-at faults are shown to be enhanced relative to conventional interpolation without requiring hardware redundancy.

/pdf/probabilistic-interpolation-recoder-for-energy-error-product-45gdqi5ocv.pdf

Shadi Sheikhfaal

Papers

Designing efficient QCA logical circuits with power dissipation analysis

Towards ultra-efficient QCA reversible circuits

ApGAN: Approximate GAN for Robust Low Energy Learning From Imprecise Components

Designing High Speed Sequential Circuits by Quantum-Dot Cellular Automata: Memory Cell and Counter Study

Probabilistic Interpolation Recoder for Energy-Error-Product Efficient DBNs with p-bit Devices