S
Shen-Yu Peng
Researcher at National Chiao Tung University
Publications - 12
Citations - 201
Shen-Yu Peng is an academic researcher from National Chiao Tung University. The author has contributed to research in topics: Dynamic voltage scaling & Power management. The author has an hindex of 7, co-authored 12 publications receiving 179 citations. Previous affiliations of Shen-Yu Peng include Industrial Technology Research Institute.
Papers
More filters
Journal ArticleDOI
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement
Yu-Huei Lee,Shen-Yu Peng,Chao-Chang Chiu,Alex Chun-Hsien Wu,Ke-Horng Chen,Ying-Hsi Lin,Shih-Wei Wang,Tsung-Yen Tsai,Chen-Chih Huang,Chao-Cheng Lee +9 more
TL;DR: A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC).
Journal ArticleDOI
Orientation relationships among m23c6, m6c, and austenite in an fe-mn-al-mo-c alloy
TL;DR: In this article, the orientation relationship between M6C and the austenite phase was determined by means of transmission electron microscopy and diffraction techniques, and the orientation relationships among M23C6, Mi6C, and M4C were determined as follows: {fx567-1}
Journal ArticleDOI
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System
Yu-Huei Lee,Chao-Chang Chiu,Shen-Yu Peng,Ke-Horng Chen,Ying-Hsi Lin,Chao-Cheng Lee,Chen-Chih Huang,Tsung-Yen Tsai +7 more
TL;DR: Experimental results show that the SIDO power module achieves a peak efficiency of 90% and the highest power reduction of 33% with the proposed near-optimum DVS operation.
Journal ArticleDOI
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings
Shen-Yu Peng,Tzu-Chi Huang,Yu-Huei Lee,Chao-Chang Chiu,Ke-Horng Chen,Ying-Hsi Lin,Chao-Cheng Lee,Tsung-Yen Tsai,Chen-Chih Huang,Long-Der Chen,Cheng-Chen Yang +10 more
TL;DR: Results show that the iD VS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition.
Proceedings ArticleDOI
A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance
Yu-Huei Lee,Shen-Yu Peng,Alex Chun-Hsien Wu,Chao-Chang Chiu,Yao-Yi Yang,Ming-Hsin Huang,Ke-Horng Chen,Ying-Hsi Lin,Shih-Wei Wang,Ching-Yuan Yeh,Chen-Chih Huang,Chao-Cheng Lee +11 more
TL;DR: A 50nA quiescent current asynchronous digital-LDO (DLDO) integrated with the PLL-modulated switching regulator (SWR) and the leading phase amplifier achieves on-the-fly DVS and 94% peak efficiency, as well as improves 5.6 times MIPS performance through hybrid operation.