K
Ke-Horng Chen
Researcher at National Chiao Tung University
Publications - 388
Citations - 5078
Ke-Horng Chen is an academic researcher from National Chiao Tung University. The author has contributed to research in topics: Voltage & Buck converter. The author has an hindex of 35, co-authored 354 publications receiving 4489 citations. Previous affiliations of Ke-Horng Chen include University College of Engineering & Realtek.
Papers
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Journal ArticleDOI
Single-Inductor Multi-Output (SIMO) DC-DC Converters With High Light-Load Efficiency and Minimized Cross-Regulation for Portable Devices
Ming-Hsin Huang,Ke-Horng Chen +1 more
TL;DR: A new delta-voltage generator can automatically switch the operating mode from pulse width modulation (PWM) mode to hysteresis mode, thereby avoiding inductor current accumulation when the total power of the buck output terminals is larger than that of the boost output terminals.
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Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications
TL;DR: A highly efficient tri-mode DC-DC converter is invented in this paper for system-on-chip (SoC) applications, which is switched to sleeping mode at very light load condition or to high-speed mode at heavy load condition.
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A Li-Ion Battery Charger With Smooth Control Circuit and Built-In Resistance Compensator for Achieving Stable and Fast Charging
TL;DR: A built-in resistance compensator (BRC) technique is presented to speed up the charging time of a lithium-ion battery and the period of the CC stage can be extended to 40% of that of the original design.
Journal ArticleDOI
Hybrid Buck–Boost Feedforward and Reduced Average Inductor Current Techniques in Fast Line Transient and High-Efficiency Buck–Boost Converter
TL;DR: In this article, a buck-boost converter with high efficiency and small output ripple is proposed to extend the battery life of portable devices, and the hybrid buck-Boost feedforward (HBBFF) technique is integrated in this converter to achieve fast line response.
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A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement
Yu-Huei Lee,Shen-Yu Peng,Chao-Chang Chiu,Alex Chun-Hsien Wu,Ke-Horng Chen,Ying-Hsi Lin,Shih-Wei Wang,Tsung-Yen Tsai,Chen-Chih Huang,Chao-Cheng Lee +9 more
TL;DR: A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC).