International Journal of Computer and Applications

An improved DWT-SVD domain watermarking for medical information security

Resistive random access memory (RRAM) devices are receiving increasing extensive attention due to their enhanced properties such as fast operation speed, simple device structure, low power consumption, good scalability potential and so on, and are currently considered to be one of the next-generation alternatives to traditional memory. In this review, an overview of RRAM devices is demonstrated in terms of thin film materials investigation on electrode and function layer, switching mechanisms and artificial intelligence applications. Compared with the well-developed application of inorganic thin film materials (oxides, solid electrolyte and two-dimensional (2D) materials) in RRAM devices, organic thin film materials (biological and polymer materials) application is considered to be the candidate with significant potential. The performance of RRAM devices is closely related to the investigation of switching mechanisms in this review, including thermal-chemical mechanism (TCM), valance change mechanism (VCM) and electrochemical metallization (ECM). Finally, the bionic synaptic application of RRAM devices is under intensive consideration, its main characteristics such as potentiation/depression response, short-/long-term plasticity (STP/LTP), transition from short-term memory to long-term memory (STM to LTM) and spike-time-dependent plasticity (STDP) reveal the great potential of RRAM devices in the field of neuromorphic application.

https://www.mdpi.com/2079-4991/10/8/1437/pdf

Advances of RRAM Devices: Resistive Switching Mechanisms, Materials and Bionic Synaptic Application.

With the widespread growth of medical images and improved communication and computer technologies in recent years, authenticity of the images has been a serious issue for E-health applications. In order to this, various notable watermarking techniques are developed by potential researchers. However, those techniques are unable to solve many issues that are necessary to be measured in future investigations. This paper surveys various watermarking techniques in medical domain. Along with the survey, general concepts of watermarking, major characteristics, recent applications, concepts of embedding and recovery process of watermark, and the summary of various techniques (in tabular form) are highlighted in brief. Further, major issues associated with medical image watermarking are also discussed to find out research directions for fledgling researchers and developers.

Watermarking techniques for medical data authentication: a survey

On Degree Based Topological Properties of Two Carbon Nanotubes

the present time, great emphasis has been given to the design of low-power and high performance memory circuits. As an SRAM is a critical component in both high-performance processors and hand-held portable devices. So the ever-increasing levels of on-chip integration of SRAM, offers serious design challenges in terms of power requirement and cell stability. There is a significant increase in the sub-threshold leakage due to its exponential relation to the threshold voltage, and gate leakage due to the reducing gate-oxide thickness. In order to minimize the leakage current, the supply voltage is reduced drastically which reduces the threshold voltage of the cell.This reduces the threshold voltage of the cell which results in reduction of the Static Noise Margin (SNM) of the cell and affect the data stability of the cell, seriously. In this work, the solutions for theses two problems, in the conventional 6T SRAM Cell has been explored.

/pdf/static-noise-margin-analysis-of-various-sram-topologies-1nfm3d787i.pdf

Static Noise Margin Analysis of Various SRAM Topologies

The emerging Wireless Sensor Network technologies are facilitating novel applications in health monitoring, industrial monitoring and security surveillance. The small physical dimensions of wireless sensor nodes often restrict the energy source to a small battery. The limited energy consumption requirement demands for ultra-low power sensing, processing and communication. This paper targets the modeling and simulation of CMOS leakage currents and its minimization approach to reduce the power consumption by a single cell SRAM cache. The popular approaches for leakage reduction are the data retention gated ground, and dynamic threshold voltage for cache. The work focuses on the simulation of a SRAM Cell for the data retention gated ground and drowsy mode SRAM Cell which shows that the current reduction of around 25% in s simulation model, respectively in comparison with the conventional cell with no current reduction technique.

Leakage Current Reduction in 6T Single Cell SRAM at 90nm Technology

—For mobile and multimedia applications of SRAMs, there is a strong need to reduce standby current leakages while keeping the memory cell data unchanged. To meet this objective, various techniques have been developed to reduce the leakage current at the process/device, circuit, architecture, and algorithmic levels. The traditional 6T CMOS SRAMs face many challenges in deep-submicron (DSM) technologies for low supply voltage (VDD) operation. Predictions suggests that process variations will limit standard 90nm SRAMs to around 0.7V operation because of the Static Noise Margin (SNM) degradation and write margin, also a VDD of 0.7V is reported for a 65nm SRAM. This work discusses some of the schemes that minimizes the cell leakage regardless of the process fluctuations and the environmental conditions. Various SRAM leakage currents identifies the suitable schemes for 6T SRAM sub-threshold operation at device and circuit levels for optimal sub-threshold circuit designs and provides an effective roadmap for digital circuit designers who are interested to work with ultra-low-power applications in CMOS technology.

Analysis of the Effects of the Operating Temperature at the Performance and Leakage Power Consumption in a Conventional CMOS 6T-SRAM Bit-Cell at 65nm, 45nm, and 32nm Technologies

Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM

The growing demand of multimedia rich applications in handled portable devices continuously driving the need for large and high speed embedded Static Random Access Memory (SRAM) to enhance the system performance. Many circuit techniques, e.g. body bias, bit charge recycling etc., have been proposed to expand design margins at low voltage operation while reducing leakage current at standby mode, but the performance is analyzed at the cost of speed and this issue is not addressed widely. Also due to continuous scaling of CMOS, the process variations also affect the performance of SRAMs. This paper presents the analysis of low leakage SRAM along with the speed factor.

/pdf/speed-and-leakage-power-trade-off-in-various-sram-circuits-i4azitlb0g.pdf

Shilpi Birla

Papers

Static Noise Margin Analysis of Various SRAM Topologies

Leakage Current Reduction in 6T Single Cell SRAM at 90nm Technology

Analysis of the Effects of the Operating Temperature at the Performance and Leakage Power Consumption in a Conventional CMOS 6T-SRAM Bit-Cell at 65nm, 45nm, and 32nm Technologies

Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM

Speed and Leakage Power Trade-off in Various SRAM Circuits