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Shinsuke Harada
Researcher at National Institute of Advanced Industrial Science and Technology
Publications - 183
Citations - 2171
Shinsuke Harada is an academic researcher from National Institute of Advanced Industrial Science and Technology. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 22, co-authored 169 publications receiving 1709 citations.
Papers
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Journal ArticleDOI
Crystal-orientation-dependent flatband voltage of non-polar GaN MOS interfaces investigated using trench sidewall capacitors
TL;DR: In this article, the flatband voltage was found to be higher on the m-face trench than on the a-face one, and an interface state density of ∼1.5 × 1.1 cm−2 cm−1 eV−1 near the conduction band edge was achieved, irrespective of the trench direction.
Journal ArticleDOI
Comparative Study of Characteristics of Lateral MOSFETs Fabricated on 4H-SiC (11-20) and (1-100) Faces
Keiko Ariyoshi,Shinsuke Harada,Junji Senzaki,Takahito Kojima,Yusuke Kobayashi,Yasunori Tanaka,Ryosuke Iijima,Takashi Shinohe +7 more
TL;DR: In this article, the lateral MOSFETs were fabricated on (11-20) and (1-100) faces and compared the properties between these faces with various gate oxide processes.
Journal ArticleDOI
Systematic Investigation of 4H-SiC Trench Properties Dependence on Channel Concentration, Crystallographic Plane, and MOS Interface Treatment
Hidenori Kitai,Tomoaki Hatayama,Hideto Tamaso,Shinaya Kyogoku,Takeyoshi Masuda,Hiromu Shiomi,Shinsuke Harada,Kenji Fukuda +7 more
TL;DR: In this article, the trench properties of 4H-SiC for p-type channel doping level formed by epitaxial growth, crystallographic plane, and MOS interface treatment were systematically investigated.
Proceedings ArticleDOI
Edge Termination Design with Strong Process Robustness for 1.2 kV-class 4H-SiC Super Junction V-groove MOSFETs
TL;DR: In this paper, double reduced surface junction termination extensions (DRJTEs) were adopted as a new edge termination for the super junction V-groove MOSFETs in order to deplete the highly doped drift layer and current spreading layer.
Journal ArticleDOI
1360 V, 5.0 mΩcm2 Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)
Hiroshi Kono,Takuma Suzuki,Makoto Mizukami,Chiharu Ota,Shinsuke Harada,Junji Senzaki,Kenji Fukuda,Takashi Shinohe +7 more
TL;DR: In this paper, double-implanted metal-oxide-semiconductor field effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face.