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Materials Science Forum

GaN technology is not only gaining traction in power and RF electronics but is also rapidly expanding into other application areas including digital and quantum computing electronics. This paper provides a glimpse of future GaN device technologies and advanced modeling approaches that can push the boundaries of these applications in terms of performance and reliability. While GaN power devices have recently been commercialized in the 15–900 V classes, new GaN devices are greatly desirable to explore both higher-voltage and ultra-low-voltage power applications. Moving into the RF domain, ultra-high frequency GaN devices are being used to implement digitized power amplifier circuits, and further advances using the hardware–software co-design approach can be expected. On the horizon is the GaN CMOS technology, a key missing piece to realize the full-GaN platform with integrated digital, power, and RF electronics technologies. Although currently a challenge, high-performance p-type GaN technology will be crucial to realize high-performance GaN CMOS circuits. Due to its excellent transport characteristics and ability to generate free carriers via polarization doping, GaN is expected to be an important technology for ultra-low temperature and quantum computing electronics. Finally, given the increasing cost of hardware prototyping of new devices and circuits, the use of high-fidelity device models and data-driven modeling approaches for technology-circuit co-design are projected to be the trends of the future. In this regard, physically inspired, mathematically robust, less computationally taxing, and predictive modeling approaches are indispensable. With all these and future efforts, we envision GaN to become the next Si for electronics.

Emerging GaN technologies for power, RF, digital, and quantum computing applications: Recent advances and prospects

FinFET is the backbone device technology for CMOS electronics at deeply scaled technology nodes per Moore’s law. Recently, the FinFET concept has been leveraged to develop a new generation of vertical power transistors based on wide-bandgap (WBG) and ultrawide-bandgap (UWBG) semiconductors for kilovolts and high-power applications. The sidewall gate-stack in a vertical power FinFET can rely on either a metal–oxide–semiconductor (MOS) structure or a p-n junction, rendering a Fin-MOSFET or a fin-based junction field-effect transistor (Fin-JFET), respectively. Although the device technologies are still at the early stage of development, 1.2-kV-class WBG gallium nitride (GaN) power Fin-MOSFETs have demonstrated one of the highest static and switching performances in all similarly rated power transistors; UWBG gallium oxide power Fin-MOSFETs have shown high performance up to a breakdown voltage over 2.6 kV. Early UWBG diamond lateral power Fin-MOSFETs have also been demonstrated. Meanwhile, GaN power Fin-JFETs are currently under active development. This article provides a comprehensive tutorial and review of the background and recent advances in WBG and UWBG vertical power FinFETs. It covers fundamental device physics, device and process development, as well as the static and switching performance of various power Fin-MOSFETs and Fin-JFETs. This article is concluded by identifying the current challenges and exciting research opportunities in this very dynamic research field.

(Ultra)Wide-Bandgap Vertical Power FinFETs

This work describes the high-temperature performance and avalanche capability of normally- off 1.2-K V-CLASS vertical gallium nitride (GaN) fin-channel junction field-effect transistors (Fin-JFETs). The GaN Fin-JFETs were fabricated by NexGen Power Systems, Inc. on 100-mm GaN-on-GaN wafers. The threshold voltage ( ${V}_{\text {TH}}$ ) is over 2 V with less than 0.15 V shift from 25 °C to 200 °C. The specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) increases from 0.82 at 25 °C to 1.8 $\text{m}\Omega \cdot $ cm2 at 200 °C. The thermal stability of ${V}_{\text {TH}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}$ are superior to the values reported in SiC MOSFETs and JFETs. At 200 °C, the gate leakage and drain leakage currents remain below $100~\mu \text{A}$ at −7-V gate bias and 1200-V drain bias, respectively. The gate leakage current mechanism is consistent with carrier hopping across the lateral p-n junction. The high-bias drain leakage current can be well described by the Poole–Frenkel (PF) emission model. An avalanche breakdown voltage ( $BV_{\!\!\text {AVA}}$ ) with positive temperature coefficient is shown in both the quasi-static ${I}$ – ${V}$ sweep and the unclamped inductive switching (UIS) tests. The UIS tests also reveal a $BV_{\!\!\text {AVA}}$ over 1700 V and a critical avalanche energy ( ${E}_{\text {AVA}}$ ) of 7.44 J/cm2, with the ${E}_{\text {AVA}}$ comparable to that of state-of-the-art SiC MOSFETs. These results show the great potentials of vertical GaN Fin-JFETs for medium-voltage power electronics applications.

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1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

Integration of SBD into SiC-MOSFET is promising to solve body-PiN-diode related problems known such as forward degradation and reverse recovery loss Particularly in lower breakdown-voltage-class SBD-integrated MOSFET, cell pitch reduction has a greater impact on inactivating the body-PiN-diode Here, we developed a novel device called an SBD-wall-integrated trench MOSFET (SWITCH-MOS), in which small cell pitch of 5pm was realized by utilizing trench side walls both for SBD and MOS channel with buried p+ layer The fabricated 12 kV SWITCH-MOS successfully suppressed the forward degradation under extremely high current density condition with low switching loss, low specific on-resistance, and low leakage current

Body PiN diode inactivation with low on-resistance achieved by a 1.2 kV-class 4H-SiC SWITCH-MOS

A 1.2 kV-class superjunction (SJ) UMOSFET was realized using a multi-epitaxial growth method. The dynamic characteristics were characterized, and the potential of a product level device was identified for the first time. The switching characteristics with Schottky barrier diode showed no degradation in spite of the large drain-source capacitance (C DS ). The reverse recovery characteristics of the body diode exhibited a soft recovery which may originate from the large C DS and the short lifetime of minority carrier. A high short circuit capability comparable to a non-SJ device was demonstrated.

First Demonstration of Dynamic Characteristics for SiC Superjunction MOSFET Realized using Multi-epitaxial Growth Method

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at V g =25 V (E ox =3.2 MV/cm) and VG=20V (E ox =2.5 MV/cm), respectively, for the 3mm × 3mm device were 2.4 and 2.8 mΩcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mΩcm2 with a high Vth of 5.9 V.

1200 V SiC IE-UMOSFET with low on-resistance and high threshold voltage

The effect of a gate trench bottom p+ region (BPR) on the dynamic characteristics of 4H-SiC double-trench MOSFETs was investigated. Although employing a BPR led to an improved trade-off in the static characteristics, a BPR adversely affected the switching characteristics in spite of a reduction in the Miller capacitance compared to the case without a BPR. Simulation analysis revealed that a resistance between a BPR and a source electrode led to an increase in the switching loss. We have found reduction of the resistance is insufficient in order to provide benefits from the BPR. Hence, it is necessary to improve layouts of contacts of the BPR to the source electrode.

Role of Trench Bottom Shielding Region on Switching Characteristics of 4H-SiC Double-Trench Mosfets

We developed a silicon carbide (SiC) power module that can switch large currents at high speed. The withstand voltage of this power module is 1200 V, and two SiC MOSFETs are built-in and constitute a circuit for one inverter phase. This power module incorporates a snubber circuit for reducing the surge voltage generated by the SiC MOSFET for high-speed switching. In this study, switching at 270 A (a current density of 1000 A/cm 2 or more for the SiC MOSFET) was performed to evaluate this module. The turn-off switching time tf was ~10 ns, and the maximum dv/dt was 80 kV/us. Furthermore, this research examines the design and performance of the proposed power module.

Development of a High-Speed Switching Silicon Carbide Power Module

We have fabricated the lateral MOSFETs on (11-20) and (1-100) faces and have compared the properties between these faces with various gate oxide processes. It has been demonstrated that (11-20) and (1-100) faces show comparable electrical properties with nitridation treatment on the gate oxide. Our result indicates that both faces exhibit the similar trend of the mobility vs. Dit. Furthermore, it has been shown that NO POA is beneficial to both faces in achieving high channel mobility and suppressed Vt instability.

Yusuke Kobayashi

Papers

First Demonstration of Dynamic Characteristics for SiC Superjunction MOSFET Realized using Multi-epitaxial Growth Method

1200 V SiC IE-UMOSFET with low on-resistance and high threshold voltage

Role of Trench Bottom Shielding Region on Switching Characteristics of 4H-SiC Double-Trench Mosfets

Development of a High-Speed Switching Silicon Carbide Power Module

Comparative Study of Characteristics of Lateral MOSFETs Fabricated on 4H-SiC (11-20) and (1-100) Faces