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Shiyuan Zheng

Researcher at Hong Kong University of Science and Technology

Publications -  13
Citations -  214

Shiyuan Zheng is an academic researcher from Hong Kong University of Science and Technology. The author has contributed to research in topics: CMOS & Phase noise. The author has an hindex of 6, co-authored 11 publications receiving 167 citations.

Papers
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Journal ArticleDOI

A 21–48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications

TL;DR: A mm-wave subharmonic injection-locked (SHIL) fractional-N frequency synthesizer for wireless multiband point-to-point backhaul communications and the proposed ILFM chain employs higher-order LC tanks to generate a rippled phase response over a wide frequency range to significantly enhance the locking range and to eliminate expensive mm- wave frequency calibration loops.
Journal ArticleDOI

A CMOS WCDMA/WLAN Digital Polar Transmitter With AM Replica Feedback Linearization

TL;DR: The proposed architecture is composed of a digital interpolation filter for up-sampling of the input amplitude-control word (ACW), a 9-bit switched-capacitor array for the digital polar modulation (DPM), and a 6-bit PA array to achieve the output power range for the target applications.
Journal ArticleDOI

A WCDMA/WLAN Digital Polar Transmitter With Low-Noise ADPLL, Wideband PM/AM Modulator, and Linearized PA

TL;DR: This paper presents a single-chip digital-intensive polar transmitter for WCDMA and WLAN integrating a low-phase-noise all-digital phase-locked loop, a digitally-controlled wideband phase/amplitude modulator, and a calibration-free high-linearity power amplifier.
Proceedings ArticleDOI

A 4.1-to-6.5GHz transformer-coupled CMOS quadrature digitally-controlled oscillator with quantization noise suppression

TL;DR: In this article, a wideband quadrature digitally-controlled oscillator (QDCO) operates in Class-C mode with embedded phase shifters for better phase noise and I-Q accuracy.
Journal ArticleDOI

A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

TL;DR: A 0.9–5.8-GHz receiver RF front-end integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented.