A flat-cell ROM array reduces the number of block select transistors utilized, allows for the layout of straight metal lines, while sharing the metal lines between even and odd banks, and achieves very high density and high performance. Parallel buried diffusion regions are deposited in the substrate. A gate oxide is laid over the substrate. A plurality of polysilicon word lines are laid over the gate oxide perpendicular to the buried diffusion regions, so that the areas between the respective pairs of buried diffusion regions and under the polysilicon word lines, form columns of flat cell field effect transistors. An insulating layer is laid over the polysilicon word lines, and a plurality of metal bit lines and virtual ground lines is deposited. These metal lines are shared by even and odd columns of field effect transistors. Access to the metal lines is made through a plurality of LOCOS block select transistors connected to every other buried diffusion bit line. The alternate buried diffusion bit lines are connected through either a buried diffusion region to its left or a buried diffusion region to its right to the metal lines, by means of bank right and left select transistors.

Flat-cell read-only-memory integrated circuit

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

A static random access memory with a double vertical channel structure capable of providing a highly integrated memory element and a method of the same. On a substrate of a first conductivity type, first and second layers of the same conductivity type are formed, in order. On respective surfaces of the three layers, impurity diffusion regions are formed, centers of which are located on a vertical line. The first layer having the second impurity diffusion region and the second layer having the third impurity diffusion region are removed at their center portions, except for their opposite side portions, thereby forming trenches. In these trenches, gate electrodes and a ground electrode are formed. Accordingly, the first impurity diffusion region and the remaining opposite side portions of second and third impurity diffusion regions become source/drain regions, while the remaining opposite side portions of first and second layers become a double vertical channel region.

Method of constructing a reduced size highly integrated static random access memory with double vertical channel structure

A region of a semiconductor MOS integrated circuit consists essentially of mutually parallel and spaced-apart cell rows with three successive levels of interconnections: (1) a first level (117), typically polysilicon, in which conducting stripes are confined essentially to areas overlying the cell rows; (2) a second level (116, 121), typically aluminum, in which conducting stripes run perpendicular to the cell row direction; and (3) a third level (120, 122), typically aluminum, in which conducting stripes run parallel to the row direction. In this way, the lengths of all (relatively high resistivity) first level interconnections can be made relatively short, without either crowding or complicating the layout of the second and third levels.

Three-level interconnection scheme for integrated circuits.

A read-only semiconductor memory device including memory elements arranged in a principal surface of the semiconductor substrate in a matrix to form MOS transistors. Each of the memory elements has first and second electrode regions formed in the principal surface so as to respectively constitute the first and second electrodes, insulative layers formed on the principal surface, and a control electrode layer formed via the insulative layers on the principal surface to constitute the control electrode. The control electrode layer is commonly connected to memory elements in the lateral direction of the matrix. The first and second electrode regions are respectively arranged such that any adjacent two in the vertical direction of the memory elements electrically share the first and second electrodes, respectively. Each of the first electrode regions is interconnected to the first electrode region of one of the elements adjacent thereto in the lateral direction. The second electrode regions are also interconnected similarly. The device further includes first and second conductor members each formed on the insulative layers so as to electrically interconnect the first and second electrode regions, respectively, of the elements in the vertical direction. The boundaries between the control electrode layer and the first and second electrodes are defined in the lateral direction substantially in parallel thereto.

Nonvolatile semiconductor memory device of shared contact scheme not having inclined wiring

A read-only memory has word lines (9) and ground tines (10) extending linearly and parallel to each other above a semiconductor substrate, and data lines (11) extending perpendicularly to the word lines (9) The data lines are connected via connection (24) to impurity regions 14 in the substrate, which regions (14) are drains of MOS transistors being the data storage elements of the memory The sources of the MOS transistors are formed by impurity regions (141) connected via connections 23 to the ground lines (10), and the word lines (9) extend over the gates of the transistors This structure enables a very compact memory to be achieved, thereby permitting a high integration density, with a low parasitic capacitance and parasitic resistance In one embodiment, the word and ground lines (9, 10) are formed by a common metal layer, whilst in a second embodiment the ground and data lines are formed by a common metal layer

Read-only memory

PURPOSE:To obtain the titled element of stable electric characteristics with a small required area by a method wherein a high-resistant polycrystalline Si element is vertically formed on the side wall of a deep hole of a semiconductor substrate via insulation film, and power is supplied to the high-resistant element from the substrate by contacting the element with the substrate at the bottom of the hole. CONSTITUTION:A P type well region 10 is formed on the surface of the N type Si substrate 9, and a high-concentration N type region 11 serving as the drain region is formed. The deep hole 12 reaching the substrate 9 is formed, and the insulation film 13 is formed on the side wall of the deep hole, which side wall is coated with high-resistant polycrystalline Si 14. The bottom of the Si 14 is in contact with the substrate 9, and therefore power can be supplied to the Si 14 from the substrate 9. Besides, an N type high-concentration region 15 formed above the Si 14 is connected to the drain region 11 with a wiring 16; thus, micro currents are supplied from the substrate 9 to the drain region 11, and the static action of a memory cell is enabled.

Shuichi Yamamoto

Papers

Read-only memory

High-resistant element