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Ryo Nagai

Researcher at Hitachi

Publications -  32
Citations -  422

Ryo Nagai is an academic researcher from Hitachi. The author has contributed to research in topics: Electrolyte & Electrode. The author has an hindex of 12, co-authored 32 publications receiving 421 citations. Previous affiliations of Ryo Nagai include Elpida Memory, Inc..

Papers
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Journal ArticleDOI

256-Mb DRAM circuit technologies for file applications

TL;DR: In this article, a self-reverse-biasing circuit for word drivers and decoders is proposed to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs.
Patent

Liquid fuel cell

TL;DR: In this paper, a unit fuel cell comprising a plurality of unit fuel cells each having a positive electrode for reducing oxygen, a negative electrode for oxidizing liquid fuel, and an electrolyte layer (10) interposed between the positive electrode (8) and the negative electrode (9), and a section (3) for storing liquid fuel (4), where power can be generated stably while reducing the size by arranging the plurality of units on the substantially same plane.
Proceedings ArticleDOI

256 Mb DRAM technologies for file applications

TL;DR: The authors describe 256-Mb DRAM (dynamic random access memory) technologies for file applications and a subthreshold-current limiting scheme for word drivers, which features subarray-by-subarray replacement instead of the conventional line- by-line replacement.
Patent

Optical data recording medium

TL;DR: In this paper, a write-once type filled up with any fillers optical data recording medium provided with recording layers for a melting and diffusion recording system is disclosed, wherein a protective layer is formed between the recording layers or between a recording layer and another plate shaped member, the protective layer being composed of a member which is not adversely effected by a melting operation and is not warped by changes of external conditions.
Proceedings ArticleDOI

An experimental 220 MHz 1 Gb DRAM

TL;DR: Two circuit technologies for a synchronously operating high-data-rate 1 Gb DRAM are presented: a distributed-column-control architecture reducing the burst-mode cycle time, and a ringing-canceling output buffer ensuring reliable high-speed data transfer.