Patent
Read-only memory
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TLDR
A read-only memory has word lines (9) and ground tines (10) extending linearly and parallel to each other above a semiconductor substrate, and data lines (11) extending perpendicularly to the word lines as mentioned in this paper.Abstract:
A read-only memory has word lines (9) and ground tines (10) extending linearly and parallel to each other above a semiconductor substrate, and data lines (11) extending perpendicularly to the word lines (9) The data lines are connected via connection (24) to impurity regions 14 in the substrate, which regions (14) are drains of MOS transistors being the data storage elements of the memory The sources of the MOS transistors are formed by impurity regions (141) connected via connections 23 to the ground lines (10), and the word lines (9) extend over the gates of the transistors This structure enables a very compact memory to be achieved, thereby permitting a high integration density, with a low parasitic capacitance and parasitic resistance In one embodiment, the word and ground lines (9, 10) are formed by a common metal layer, whilst in a second embodiment the ground and data lines are formed by a common metal layerread more
Citations
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References
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Patent
Very high density cells comprising a ROM and method of manufacturing same
Matthias L. Tam,Frank Z. Custode +1 more
TL;DR: In this article, the FETs are fabricated, their contacts extending linearly between bit lines which are preferably diffused lines, and the word line making direct contact with gates of the linear cells.
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Method of programming ROM by offset masking of selected gates
Roger S. Countryman,Paul T. Lin +1 more
TL;DR: In this article, a process for fabricating a MOS ROM which allows programming of the ROM late in the process sequence is described, where a conventional silicon gate process is used to fabricate the devices up through the step of patterning the polycrystalline silicon gate electrode.
Patent
A semiconductor memory device.
TL;DR: In this article, a static-type semiconductor memory device with a three-layer structure was proposed, where the gate-electrode wiring lines were formed by a first conductive layer of polycrystalline silicon; the word lines, the ground lines, and the power supply lines were created by a second conductive layers of aluminum; and the bit lines were constructed by a third conductivelayer of aluminum.
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TL;DR: In this article, a method of making a ROM and a two-level polycrystalline silicon RAM on a chip and encoding the ROM in later stages of the method, without adding a mask to the method is presented.