S
Siddhartha Joshi
Researcher at Northwestern University
Publications - 12
Citations - 52
Siddhartha Joshi is an academic researcher from Northwestern University. The author has contributed to research in topics: Pattern recognition (psychology) & Content-addressable memory. The author has an hindex of 4, co-authored 12 publications receiving 39 citations. Previous affiliations of Siddhartha Joshi include Fermilab.
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Journal ArticleDOI
Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis
Siddhartha Joshi,Dawei Li,Seda Ogrenci-Memik,Grzegorz Deptuch,James Hoff,Sergo Jindariani,Tiehui Liu,J. Olsen,Nhan Tran +8 more
TL;DR: This paper characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then proposes the use of a multi-Vdd design to save power and increase post-fabrication tunability.
Journal ArticleDOI
Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory
TL;DR: An aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project, which leverages emerging 3D vertical integration technology to build faster and denser Associative memory devices.
Journal ArticleDOI
End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs
TL;DR: This paper proposes a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs, and demonstrates that it can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management.
Proceedings ArticleDOI
VIPRAM_L1CMS: A 2-tier 3D architecture for pattern recognition for track finding
TL;DR: VIPRAML1CMS is a complete pipelined Pattern Recognition Associative Memory (PRAM) architecture including pattern recognition, result sparsification, and readout for Level 1 trigger applications in CMS with 15-bit wide detector addresses and eight detector layers included in the track finding.
Journal ArticleDOI
Dynamically Reconfigurable Data Readout of Pixel Detectors for Automatic Synchronization with Data Acquisition Systems.
TL;DR: A method is presented for seamlessly changing time frames and readout modes without data corruption while still ensuring that the data acquisition system (DAQ) does not need to stop and resynchronize at each change of setting, thus avoiding significant dead time.