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1. Introduction and Overview. 2. Detecting Influential Observations and Outliers. 3. Detecting and Assessing Collinearity. 4. Applications and Remedies. 5. Research Issues and Directions for Extensions. Bibliography. Author Index. Subject Index.

Regression Diagnostics: Identifying Influential Data and Sources of Collinearity

On the truck dispatching problem

Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively dark or dim silicon, i.e., either idle or significantly underclocked. As exponentially larger fractions of a chip's transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that “spend” area to “buy” energy efficiency. All of these techniques seek to introduce new forms of heterogeneity into the computational stack. We envision that ultimately we will see widespread use of specialized architectures that leverage these techniques in order to attain orders-of-magnitude improvements in energy efficiency. However, many of these approaches also suffer from massive increases in complexity. As a result, we will need to look towards developing pervasively specialized architectures that insulate the hardware designer and the programmer from the underlying complexity of such systems. In this paper, I discuss four key approaches — the four horsemen — that have emerged as top contenders for thriving in the dark silicon age. Each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits.

Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse

A recently developed computational imaging technique, X-ray ptychographic tomography, is used to study integrated circuits, and a 3D image of a processor chip with a resolution of 14.6 nm is obtained. As computer chips have become increasingly crammed with nanometre-scale devices and circuitry, new microscopy techniques that can resolve the smallest features are required to enable chip design and inspection. X-ray imaging is uniquely suited for non-destructive, high-resolution imaging and Mirko Holler et al. make use of a recently developed computational imaging technique, X-ray ptychography, to generate high-resolution three-dimensional images of integrated circuits. They test X-ray ptychography on a circuit with known features, and then apply it to an Intel processor chip manufactured in the 22-nanometre technology, obtaining detailed three-dimensional maps of the devices with a resolution down to 14.6 nanometres. This technique could be used to assist quality control during chip production. Modern nanoelectronics1,2 has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography3,4—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques5,6,7. Foreseeable developments in X-ray sources8, optics9 and detectors10, as well as adoption of an instrument geometry11 optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

High-resolution non-destructive three-dimensional imaging of integrated circuits

This article discusses about Greendroid mobile Application Processor. Dark silicon has emerged as the fundamental limiter in modern processor design. The Greendroid mobile application processor demonstrates an approach that uses dark silicon to execute general-purpose smart phone applications with less energy than today's most energy efficient designs.

The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future

Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 (see Ref [1] Kahng etal., Proc. DATE, 2009, pp. 423–428) is a widely adopted NoC power and area estimation tool, but its estimation models can have large errors (up to 185%) versus actual implementations. We present ORION3.0, an open-source tool whose parametric and nonparametric modeling methodologies fundamentally differ from ORION2.0 logic template-based approaches in that the estimation models are derived from actual physical implementation data. When compared with actual implementations, ORION3.0 models achieve average estimation errors of no more than 9.3% across microarchitecture, implementation, and operational parameters as well as multiple router RTL generators. A comprehensive suite of these methodologies has been implemented in ORION3.0 (see Ref [2] Available online: http://vlsicad.ucsd.edu/ORION3/.

ORION3.0: A Comprehensive NoC Router Estimation Tool

The International Technology Roadmap for Semiconductors (ITRS) has roadmapped technology requirements of the semiconductor industry over the past two decades. The roadmap identifies major challenges in advanced technology and leads the investment of research in a costeffective way. Traditionally, the ITRS identifies major semiconductor IC products as drivers; these set requirements for the state-of-theart semiconductor technologies. High-performance microprocessor unit (MPU-HP) for servers and consumer portable system-on-chip (SOC-CP) for smartphones are two examples. Throughout the history of the ITRS, Moore’s Law has been the main impetus for these drivers, continuously pushing the transistor density to scale at a rate of 2× per technology generation (aka “node”). However, as new requirements from applications such as data center, mobility, and context-aware computing emerge, the existing roadmapping methodology is unable to capture the entire evolution of the current semiconductor industry. Today, comprehending how key markets and applications drive the process, design and integration technology roadmap requires new system-level studies along with chip-level studies. In this paper, we extend the current ITRS roadmapping process with studies of key requirements from a system-level perspective, based on multiple generations of smartphones and microservers. We describe potential new system drivers and new metrics, and we refer to the new system-level framing of the roadmap as ITRS 2.0.

/pdf/itrs-2-0-toward-a-re-framing-of-the-semiconductor-technology-pxpr1fjqki.pdf

ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap

We've seen the quick adoption of GPUs as general-purpose computing engines in recent years, fueled by high computational throughput and energy efficiency. There is heavier integration of the CPU and GPU, including the GPU appearing on the same die, further decreasing barriers to the use of the GPU to offload the CPU. Much effort has been made to adapt GPU designs to anticipate this new partitioning of the computation space, including better programming models and more general processing units with support for control flow. However, researchers have placed little attention on the CPU and how it must adapt to this change. This article demonstrates that the coming era of CPU and GPU integration requires us to rethink the CPU's design and architecture. We show that the code the CPU will run, once appropriate computations are mapped to the GPU, has significantly different characteristics than the original code (which previously would have been mapped entirely to the CPU).

/pdf/redefining-the-role-of-the-cpu-in-the-era-of-cpu-gpu-9aworemwvq.pdf

Redefining the Role of the CPU in the Era of CPU-GPU Integration

In advanced technology nodes, physical design engineers must estimate whether a standard-cell placement is routable (before invoking the router) in order to maintain acceptable design turnaround time. Modern SoC designs consume multiple compute servers, memory, tool licenses and other resources for several days to complete routing. When the design is unroutable, resources are wasted, which increases the design cost. In this work, we develop machine learning-based models that predict whether a placement solution is routable without conducting trial or early global routing. We also use our models to accurately predict iso-performance Pareto frontiers of utilization, aspect ratio and number of layers in the back-end-of-line (BEOL) stack. Furthermore, using data mining and machine learning techniques, we develop new methodologies to generate training examples given very few placements. We conduct validation experiments in three foundry technologies (28nm FDSOI, 28nm LP and 45nm GS), and demonstrate accuracy ≥ 85.9% in predicting routability of a placement. Our predictions of Pareto frontiers in the three technologies are pessimistic by at most 2% with respect to the maximum achievable utilization for a given design in a given BEOL stack.

Siddhartha Nath

Papers

The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future

ORION3.0: A Comprehensive NoC Router Estimation Tool

ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap

Redefining the Role of the CPU in the Era of CPU-GPU Integration

BEOL stack-aware routability prediction from placement using data mining techniques